Texas Instruments TPS6594-Q1 Series, User Manual

Page: 5 / 28

www.ti.com
EVM Details
5 SLVUBT0 – December 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
TPS6594x-Q1 Evaluation Module
(1)
See Section 3.4 for applying input voltages other than VSYS_IN to the LDO regulators through J21
The GUI will run on most PC platforms and requires an available USB port. The EVM USB connector is
type-C and a type-A to type-C cable is provided with the EVM to connect to the host computer. The EVM
will enumerate as two COM ports and one additional port for the devices firmware updates. The port the
GUI should use is the ACCtrl COM port (and not the ACCtrl Console).
3 EVM Details
The following sections describe the various interfaces for measuring and controlling the configuration.
Note: the configurations are in coordination with the settings of the PMIC. It is important to understand that
both the EVM configuration and the settings of the PMIC must match. For example, if the GUI is used to
change the PMIC interface to SPI from I
2
C, then the appropriate SPI related jumpers should be in place
on J7 and J15. Please refer to the GUI User's Guide SLVUBT8 on how to update the PMIC
communication protocol.
3.1 Terminal Blocks
The terminal blocks are simple push and release terminals which can accommodate wire sizes up to 14
AWG.
Table 2 lists the terminal blocks found around the perimeter of the EVM. J6, VSYS_IN, is the input
voltage for all regulators (BUCK and LDO). (1) The remaining 5 terminal blocks are the BUCK outputs.
Table 2. Terminal Blocks
Terminal Designator Description
VSYS_IN J6 All Regulator Input (PVIN_LDOx, PVIN_Bx), 2.7 V to 5.5 V Range
BUCK1 J1 Buck 1 Output, 3.5 A Capable
BUCK2 J2 Buck 2 Output, 3.5 A Capable
BUCK3 J3 Buck 3 Output, 3.5 A Capable
BUCK4 J4 Buck 4 Output, 4 A (single phase) or 3.5 A Capable
BUCK5 J5 Buck 5 Output, 2 A Capable
3.2 Test Point Descriptions
Numerous test points are provided to access voltages and signals. All test points are designed for sensing
voltages only and are not designed to carry large DC currents.
Table 3. Test Point Descriptions
Test Point Device Pin Description
TP1 VCCA This point can be used to measure IDDQ,
when resistor R58 is removed.
TP2 VIO_IN This point can be used to measure IDDQ
when resistor R65 is removed.
TP3, TP4, TP5 GND NA
TP6 FB_B3 External voltage monitor connection.
TP7 FB_B4
TP8 GPIO10 (SYNCCLKIN) Sync Clock input, up to 4.4 Mhz
TP9 SW_B1 Test Point for the switch mode.Not
populated to reduce EMI.
TP10 SW_B2
TP11 SW_B3
TP12 SW_B4
TP13 SW_B5
TP14 GND NA