Texas Instruments TPS6594-Q1 Series User Manual Download Page 19 | Manualshive

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Schematic, Layout, and Bill of Materials

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SLVUBT0 – December 2019

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Copyright © 2019, Texas Instruments Incorporated

TPS6594x-Q1 Evaluation Module

Figure 13. Layout Ground, Layer 2

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Summary of Contents for TPS6594-Q1 Series

Page 1: ... 3 2 2 Getting Started Multiple EVM Evaluation 4 2 3 The GUI Tool 4 3 EVM Details 5 3 1 Terminal Blocks 5 3 2 Test Point Descriptions 5 3 3 Configuration Headers 6 3 4 Signal Headers 8 3 5 Stack up Headers 9 3 6 Connectors 12 3 7 EVM Control GPIO and additional regulators 12 4 Customization 12 4 1 Changing the Communication Interface 12 4 2 Changing the Phase Configuration 14 5 Additional Resource...

Page 2: ...Layer 5 22 17 Layout Bottom 23 List of Tables 1 EVM Descriptions 3 2 Terminal Blocks 5 3 Test Point Descriptions 5 4 Header J7 Description 6 5 Header J26 VBACKUP 7 6 Header J30 VIO_IN Voltage Select 7 7 Header J15 USB_3V3 VSYS VBUS GPIO1 I2C SPI 7 8 Header J8 Pullup Voltages 9 9 Header J37 Master Slave Select 11 10 EVM LED Indicators 12 11 Bill of Materials of Balance of Components 24 ...

Page 3: ...tarted and to accelerate development Table 1 EVM Descriptions EVM Part Number PMIC Device Part Number Mode NVM Phase Configuration Components on the Back Side of EVM R1 R7 J23 J24 J25 TPS659413EVM PTPS659413F0RW ERQ1 Master BUCK1 BUCK2 BUCK3 BUCK4 and BUCK5 R1 R2 R5 and R7 J23 TPS659411EVM PTPS659411F0RW ERQ1 Slave BUCK1 BUCK2 BUCK3 BUCK4 and BUCK5 R1 R2 R4 and R6 J23 J24 and J25 2 Getting Started...

Page 4: ...ovided that the total load is less than 3 W This removes the requirement for a separate supply when evaluating a number of the digital features of the PMIC with the EVM The three distinguishing characteristics of the slave EVM are the PMIC the backside components described in Figure 9 and the jumper position on J37 With the jumper on J37 placed in the slave position the ENABLE pin of the slave PMI...

Page 5: ...ommunication protocol 3 1 Terminal Blocks The terminal blocks are simple push and release terminals which can accommodate wire sizes up to 14 AWG Table 2 lists the terminal blocks found around the perimeter of the EVM J6 VSYS_IN is the input voltage for all regulators BUCK and LDO 1 The remaining 5 terminal blocks are the BUCK outputs Table 2 Terminal Blocks Terminal Designator Description VSYS_IN...

Page 6: ...communication between the MCU and the PMIC is enabled TRIG_WDG GPIO2 SDA2 SDO Open GPIO mode GPIO2 from PMIC is connected to PM7 of the MCU through a level translator TRIG_WDG GPIO2 Closed Trigger Watchdog mode GPIO2 of the PMIC should be in the Alternative function to support the watchdog trigger input signal GPIO2 from the PMIC is connected to the MCU output and TRIG_WDG GPIO2 SDA2 SDO Closed De...

Page 7: ... case Table 6 Header J30 VIO_IN Voltage Select Configuration Description Open Not Allowed 1 8 V or 3 3 V must be selected VIO Select 3 3 V Closed Default VIO_IN is 3 3 V VIO Select 1 8 V Closed VIO_IN is 1 8 V In addition to J7 and J26 the lower portion of J15 is also used for the selection of VSYS and GPIO1 Table 7 Header J15 USB_3V3 VSYS VBUS GPIO1 I2C SPI Configuration Description USB_3V3 VSYS ...

Page 8: ...to measure Power Supply Rejection Ratio PSRR on LDO3 and LDO4 All pins of J20 are connected to the VCCA and J20 is placed next to J21 to easily connect all the LDO power inputs to the VCCA this is the default jumper configuration An external power supply for the LDOs can also be applied directly to J21 Figure 3 LDO Headers NOTE J13 and J14 provide the same LDO outputs however J13 should only be us...

Page 9: ...and GPIO4 Input Type Selection Power Domain is VRTC 5 6 VOUT_LDOVINT GPIO5 and GPIO6 Output Type Selection Power Domain is VINT 3 5 Stack up Headers As shown in multiple boards can be configured into a master slave relationship 1 master and up to 5 slaves and physically stacked upon each other VCCA and GND are shared between boards on headers J27 and J28 Communication between the boards is shared ...

Page 10: ...of the PMIC are connected through J37 When multiple PMICs are stacked as shown in Figure 6 the expectation is that the master is placed in master mode connecting the stackable signal nPWRON_S and the VOUT_LDOVINT By using this stackup configuration one or more of the slaves power up sequence will always follow the master When in master mode or when the header J37 is left open the nPWRON ENABLE pin...

Page 11: ...e for Master and One or More Slaves Table 9 Header J37 Master Slave Select Configuration Description Open When used as a single PMIC no stacking ENABLE is connected to a pullup and therefore automatically enabled S1 can be used to generate edges or change the level Slave M S Select Closed Slave Mode The PMIC signal ENABLE is connected to the nPWRON_S signal which is from the master s VOUT_LDOVINT ...

Page 12: ...ranslators the TS3A5018RSVR switch is used to apply the pullup voltages to the I2 C lines only when the EVM is a master J37 The application of the pullup resistors is for I2 C mode only and is only intended for one board in a stack up application Note in the stack up configuration only one board can have a valid VBUS voltage on the board This means that the master board can have a connected USB ca...

Page 13: ...ng this jumper will connect the micro controller to the SPI bus which is connected to all available PMICs through the EVM stack connection through J29 In a multiple EVM stackup this jumper should only be placed on the EVM with the USB connection to the host computer The SPI does not have a device ID and therefor the chip select is used to determine which PMIC will receive and respond to commands o...

Page 14: ...ortant that the phase configuration of the EVM matches the phase configuration of the PMIC Specific consideration should be given to BUCK3 and BUCK4 in phase configurations 1 and 2 since these regulators have independent feedback circuits which can be configured to measure external supplies FB_B3 and FB_B4 are made available on test points TP6 and TP7 respectively If the voltage monitors associate...

Page 15: ...struments Incorporated TPS6594x Q1 Evaluation Module Figure 9 Phase Configuration Components 5 Additional Resources Programmable Processor PMIC s GUI User s Guide TPS65921 Q1 Power Management IC PMIC With 4 Phase 14 A Buck for ProcessorsTPS65921 Q1 Power Management IC PMIC With 4 Phase 14 A Buck for Processors ...

Page 16: ..._IN 48 SW_B3 44 SW_B1 27 VOUT_LDOVINT 2 VCCA 4 PVIN_B3 45 PWRON ENABLE 20 GPIO10 42 VBACKUP 36 SW_B4 56 PVIN_LDO3 10 SW_B2 16 PVIN_B5 35 FB_B5 37 SW_B4 55 FB_B2 21 AMUXOUT 1 OSC32KOUT 39 GPIO1 32 FB_B4 50 GPIO11 53 SW_B1 28 PVIN_LDO4 8 GPIO3 46 U1 2 2uF C5 2 2uF C6 VOUT_LDO4 1 2 3 4 5 J32 1 2 3 4 5 J33 1 2 3 4 5 J35 1 2 3 4 5 J34 GPIO3 GPIO4 GPIO7 GPIO8 GPIO9 GPIO11 GPIO7 nINT EN_DRV 0 R1 0 R2 0 R...

Page 17: ...ND 55 GND 58 VBAT 68 VDD 69 VDD 79 GND 80 VDDC 87 VDD 90 VDD 101 VDD 113 GND 114 VDDC 115 VDD 122 MSP432E401YTPDTR U3D 4 87k R43 4 87k R41 SDA_I2C2 SDO_SPI SCL_I2C1 SCK_SPI SDA2 SCL2 SDA1 SDI SDA2 SDO SDA_I2C1 SDI_SPI nPWRON_S IO1 IO11 nINT3P3 100 R45 1 0M R68 1 0M R69 1 0M R60 2 2uF C85 2 2uF C86 2 2uF C88 1 0k R61 1 2k R50 SCL_I2C1 SCK_SPI 2 2uF C91 VCC3P3 2 2uF C97 2 2uF C96 2 2uF C81 VIO_IN MC...

Page 18: ...matic Layout and Bill of Materials www ti com 18 SLVUBT0 December 2019 Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated TPS6594x Q1 Evaluation Module Figure 12 Layout Top Layer 1 ...

Page 19: ...i com Schematic Layout and Bill of Materials 19 SLVUBT0 December 2019 Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated TPS6594x Q1 Evaluation Module Figure 13 Layout Ground Layer 2 ...

Page 20: ...atic Layout and Bill of Materials www ti com 20 SLVUBT0 December 2019 Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated TPS6594x Q1 Evaluation Module Figure 14 Layout Signal Layer 3 ...

Page 21: ...i com Schematic Layout and Bill of Materials 21 SLVUBT0 December 2019 Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated TPS6594x Q1 Evaluation Module Figure 15 Layout Signal Layer 4 ...

Page 22: ...atic Layout and Bill of Materials www ti com 22 SLVUBT0 December 2019 Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated TPS6594x Q1 Evaluation Module Figure 16 Layout Ground Layer 5 ...

Page 23: ...ww ti com Schematic Layout and Bill of Materials 23 SLVUBT0 December 2019 Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated TPS6594x Q1 Evaluation Module Figure 17 Layout Bottom ...

Page 24: ...R70J476ME 19L C36 C47 C58 C69 C78 5 10 µf CAP CERM 10 µf 16 V 10 X7S AEC Q200 Grade 1 0805 0805 CGA4J1X7S1C106K 125AC C45 C46 C48 C49 C50 C51 C52 C53 C56 C57 10 Chip Multilayer Ceramic Capacitors for Automotive 1206 3216 Metric GCM31CD70G476M E C54 C55 C59 C60 C61 C62 C63 C64 C65 C66 10 10 µf CAP CERM 10 µF 4 V 20 1 6x0 8 mm 1 6x0 8 mm NFM18HC106D0G3 C67 C68 C70 C71 C72 C73 C74 C75 C76 C77 C84 11 ...

Page 25: ...in Film 470 nH 5 3 A 0 021 Ω AEC Q200 Grade 0 SMD TDK Inductor TFM322512ALMAR4 7MTAA LBL1 1 PCB Label 0 650 x 0 200 in THT 14 423 10 MP1 MP2 MP3 MP4 4 SPACER FC2058 440 A Q1 1 30 V MOSFET N CH 30 V 27 2 A AEC Q101 SO 8FL SO 8FL NVMFS4C05NT1G R1 R2 R4 R6 R19 R26 R35 R36 R39 R40 R58 R65 R67 R83 14 0 RES 0 5 0 063 W AEC Q200 Grade 0 0402 0402 RK73Z1ETTP R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R27 R...

Page 26: ...iniature Red TH Red Miniature Testpoint 5000 TP3 TP4 TP5 TP14 4 PC Test Point SMT PC Test Point SMT 5017 TP6 TP7 TP8 3 Test Point Miniature Yellow TH Yellow Miniature Testpoint 5004 U1 1 Power Management IC PMIC With 4 Phase 14 A Buck for Processors RVJ0056A VQFN 56 RVJ0056A TPS65941 Q1 U2 1 AEC Q100 Quad Comparator PW0014A TSSOP 14 PW0014A LM2901AVQPWRQ1 U3 1 MSP432E401YTPDT PDT0128A TQFP 128 PDT...

Page 27: ...1X7R0J226M 160AC C3 0 47000 µf CAP Electric Double Layer 47000 µf 5 5 V 80 20 TH Horizontal D11 5x5 mm DX 5R5H473U C79 0 680 µf CAP TA 680 µF 6 3 V 10 0 023 Ω AEC Q200 Grade 1 SMD 7343 40 T510X687K006AGA0 23 FID6 0 Fiducial mark There is nothing to buy or mount N A N A J16 J17 0 Receptacle 2 5 mm 3x2 Gold SMT Receptacle 2 5 mm 3x2 SMT 6651712 1 J32 J33 J34 J35 J36 0 SMA Jack Straight 50 Ω Gold TH ...

Page 28: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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