The programming control shown in
provides all the power and controls that may be needed. The
actual number of connections needed will vary by usage. If there is an MCU on the board that is not powered by
the PMIC, the programming controls would also depict what signals need to be active when the MCU is updating
the PMIC.
To enable SPI interface, by pull GPIO3 high after powering VCCA and VIO_IN.
GPIO4 is available to enable CRC on the I2C or SPI interface. This aids in the scenario when the host MCU or
software is expecting a CRC value to be included with register reads and writes.
For multi-PMIC solutions, GPIO10 can be used to change the I2C1 address from 0x28 to 0x2C. If all the I2C
lines of multi-PMIC solutions are tied together, it is required that the device being programmed has unique I2C
addresses. For this functionality, GPIO10 can be pulled high to update the I2C1 address before a PMIC is
programmed. Then, the next PMIC in the system can utilize GPIO10 to update its I2C address to the unique
address of 0x2C for programming, and so on until all PMICs are programmed with custom settings and unique
I2C addresses. PMICs not in the process of being programmed would keep GPIO10 low, to ensure that they are
not being addressed on the 0x2C address.
The ENABLE pin is only required to be pulled high if the default interface settings need to be updated. If no
interface settings are required, keep this pin low. It is expected that after the device is programmed with initial
custom settings, ENABLE would always remain low during programming to ensure all outputs of the PMIC are
disabled.
Lastly, VIO_IN of the PMICs must be supplied to support I2C or SPI communication during programming. If VIO
is normally enabled or supplied by an output of the PMIC (either a regulator or GPIO), it is recommended to
externally supply VIO while making NVM updates. All regulators and GPIOs, excluding SPI communication on
GPIO1 and GPIO2, are automatically disabled during NVM programming.
4 Static NVM Settings
The TPS6593-Q1 device consists of fixed registers and configurable registers that are loaded from NVM. For all
NVM registers, the initial NVM settings that load into the registers are provided in this section. Note: these initial
NVM settings, unless stated otherwise, can be changed once the PMICs have transitioned into ACTIVE state.
The full register map, including default values of fixed registers, is located in the TPS6593-Q1 datasheet.
4.1 Application-Based Configuration Settings
In the TPS6593-Q1 data sheet, there are multiple application-based configurations for each BUCK to operate
within.
includes the different configurations available:
Table 4-1. TPS6593-Q1 Use Cases
TPS6593-Q1
2.2 MHz Single Phase for DDR Termination
4.4 MHz Multiphase Configuration
4.4 MHz Single Phase Low Output Voltage
4.4 MHz Single Phase High Output Voltage
2.2 MHz Multiphase with Full Range VIN
2.2 MHz Single Phase with 5.0 V VIN
2.2 MHz Single Phase with Full Range VIN
The seven configurations also have optimal output inductance values that optimize the performance of each
buck under these various conditions.
shows the default configurations for the BUCKs. These settings
cannot be changed after device startup. These settings can be changed through reprogramming of the NVM.
Static NVM Settings
4
Programmable PMICs: TPS6593-Q1 Default Configuration for TPS6593EVM
SLVUC24 – MAY 2021
Copyright © 2021 Texas Instruments Incorporated
