Texas Instruments TPS65735EVM-703 User Manual Download Page 5

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Connector and Test Point Descriptions

4

Connector and Test Point Descriptions

4.1

Headers and Switch

J1 : VIN
J1 pin 1 and pin 2 are VIN of the TPS65735. Connect the VIN (Charger) power supply positive terminal to
J1.

J2 : GND
J2 pin 1 and pin 2 are GND of the TPS65735. Connect the VIN (Charger) power supply negative terminal
to J2.

J3 : BAT
J3 pin 1 and pin 2 are BAT of the TPS65735. Connect the second power supply (Battery)(capable of
sinking current) positive terminal to J3.

J4 : GND
J4 pin 1 and pin 2 are GND of the TPS65735. Connect the second power supply (Battery)(capable of
sinking current) negative terminal to J4.

J5 : GND
J5 pin 1 and pin 2 are GND of the TPS65735. These are provided as an extra set of ground terminals.

J6 : LP, LN
J6 pin 1 is LCLP, liquid crystal left positive, of the TPS65735 and pin 2 is LCLN, liquid crystal left negative,
of the TPS65735. Connect the left lens across pin 1 and 2 of header J6.

J7 : RP, RN
J7 pin 1 is LCRP, liquid crystal right positive, of the TPS65735 and pin 2 is LCRN, liquid crystal right
negative, of the TPS65735. Connect the left lens across pin 1 and 2 of the J7.

J8 : BST_OUT
J8 pin 1 and pin 2 are BST_OUT of the TPS65735. In a typical application, the boost will be loaded only
through the h-bridge on pins LCLP, LPLN, LCRP,LCRN (J6,J7) by the liquid crystal lenses.

J9 : GND
J9 pin 1 and pin 2 are GND.

J10 : VLDO, GND
J10 pin 1 is GND and pin 2 is VLDO, the output of the TPS65735 LDO.

J11 (3-pin header): SWITCH, HIGH, LOW
J11 pin 1 is GND, pin 2 is the SWITCH pin of the TPS65735 and pin 3 is the SYS voltage output of the
TPS65735. This header, J11, is to simulate the use of a slide switch and should only be used when JP1
pins 1 and 2 are shorted. If instead, a push-button switch is used, J11 should be left open and the
push-button will pull SWITCH to GND when pressed and release (float) it otherwise (SWITCH has an
internal pull-up only when JP1 pins 2 and 3 are shorted). Note there is an alternate configucation for J11.

J11 (2-pin header): SWITCH (alternate configuration)
J11 pin 1 is GND, pin 2 is the SWITCH pin of the TPS65735. This header, J11, is to simulate the use of a
slide switch and should only be used when JP1 pins 1 and 2 are shorted. To simluated the use of a slide
switch the switch pin of the TPS65735 must be connected to SYS (HIGH) to keep the device on and
connected to ground to turn the device off. If instead, a push-button switch is used, J11 should be left
open and the push-button will pull SWITCH to GND when pressed and release (float) it otherwise
(SWITCH has an internal pull-up only when JP1 pins 2 and 3 are shorted).

S1: Push-Button Switch
S1 is the push-button switch connected to the SWITCH pin of the TPS65735. When the button on S1 is
pressed, the SWITCH pin is connected to ground for the duration that the button is held. When the button
is released, the SWITCH pin goes back up to SYS. S1 should only be used if JP1 is in the S1 position (pin
2 and pin 3 shorted of JP1).

J12 : TS, GND
J12 pin 1 is GND, pin 2 is the TS pin of the TPS65735. This header, J12, is to connect an external
thermistor to the TPS65735 and should be left floating if not used.

5

SLVU418

June 2011

TPS65735 System Evaluation Board

Submit Documentation Feedback

Copyright

©

2011, Texas Instruments Incorporated

Summary of Contents for TPS65735EVM-703

Page 1: ...chematic 4 2 Boost Output Ripple Vbat 3 2 V and 1 mA Load on Boost 7 3 Startup Vin 5 V 1 mA Load on Boost and 15 mA Load on LDO 8 4 Shutdown Vin 5 V 1 mA Load on Boost and 15 mA Load on LDO 8 5 Startu...

Page 2: ...formance Bottom Side 15 18 Top Assembly Silkscreen 16 19 Top Layer 16 20 Bottom Layer 17 List of Tables 1 Bill of Materials 18 2 Evaluation Materials 18 2 TPS65735 System Evaluation Board SLVU418 June...

Page 3: ...1 3 Requirements In order to operate this EVM properly the hardware must be connected and properly configured All components and connectors are installed on the EVM as shipped except the dc power sup...

Page 4: ...Schematic www ti com 3 Schematic Figure 1 Schematic 4 TPS65735 System Evaluation Board SLVU418 June 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated...

Page 5: ...pin 3 is the SYS voltage output of the TPS65735 This header J11 is to simulate the use of a slide switch and should only be used when JP1 pins 1 and 2 are shorted If instead a push button switch is us...

Page 6: ...and pin 3 is VLDO of the TPS65735 Short pins 1 and 2 to disable the boost converter or short pins 2 and 3 to enable the boost converter 4 3 Test Points TP1 When R5 is replaced with a 50 resistor TP1 i...

Page 7: ...inking at least 500mA on BAT to 3 6 V and power on Verify that input current is less than 200mA with input voltage of 5 V VIN power supply Verify D1 lights up to indicate charging 6 TPS65735EVM Test D...

Page 8: ...up Vin 5 V 1 mA Load on Boost and 15 mA Load on LDO Figure 4 Shutdown Vin 5 V 1 mA Load on Boost and 15 mA Load on LDO 8 TPS65735 System Evaluation Board SLVU418 June 2011 Submit Documentation Feedbac...

Page 9: ...Vbat 3 6 V 1 mA Load on Boost and 15 mA Load on LDO Figure 6 Shutdown Vbat 3 6 V 1 mA Load on Boost and 15 mA Load on LDO 9 SLVU418 June 2011 TPS65735 System Evaluation Board Submit Documentation Feed...

Page 10: ...om Figure 7 Switchnode Vbat 3 6 V No Load 0 5 s div Figure 8 Switchnode Vbat 3 6 V No Load 10 s div 10 TPS65735 System Evaluation Board SLVU418 June 2011 Submit Documentation Feedback Copyright 2011 T...

Page 11: ...nt Constant 15 mA Load on LDO CH3 Bstout CH4 IBOOST Figure 10 Load Transient Boost Vbat 3 6 V with 5 mA to 0mA Transient Constant 15 mA Load on LDO CH3 Bstout CH4 IBOOST 11 SLVU418 June 2011 TPS65735...

Page 12: ...6 V with 0 mA to 30 mA Transient CH3 VLDO CH4 IVLDO Figure 12 Load Transient LDO Vbat 3 6 V with 30 mA to 0 mA Transient CH3 VLDO CH4 IVLDO 12 TPS65735 System Evaluation Board SLVU418 June 2011 Submit...

Page 13: ...3 Function Generator Input to HBR2 Ch 4 LCRN output Figure 14 H Bridge Operation Ch 1 Function Generator Input to HBL1 Ch 2 LCLP output Ch 3 Function Generator Input to HBL2 Ch 4 LCLN output 13 SLVU41...

Page 14: ...Test Data www ti com 6 2 Measured Data Figure 15 Load Regulation 6 3 Thermal Performance Figure 16 and Figure 17 show the typical thermal performance for the TPS826xx for both the top side and the bo...

Page 15: ...Top Side Figure 16 Thermal Performance Top Side 6 3 2 Bottom Side Figure 17 Thermal Performance Bottom Side 15 SLVU418 June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyrig...

Page 16: ...t www ti com 7 EVM Assembly Drawings and Layout Figure 18 Top Assembly Silkscreen Figure 19 Top Layer 16 TPS65735 System Evaluation Board SLVU418 June 2011 Submit Documentation Feedback Copyright 2011...

Page 17: ...www ti com EVM Assembly Drawings and Layout Figure 20 Bottom Layer 17 SLVU418 June 2011 TPS65735 System Evaluation Board Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated...

Page 18: ...U for Active Shutter 3D Glasses QFN 32 TPS65735RSN TI Table 2 Evaluation Materials Count RefDes Value Description Size Part Number MFR 1 D1 LTST C190CKT Diode LED Red 2 1 V 20 mA 6 mcd 0603 LTST C190C...

Page 19: ...duct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application enginee...

Page 20: ...orized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parti...

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