background image

VIN

GND

S+

5

4

1
2
3

6

J1

VGH

GND

S+

5

4

1
2
3

6

J2

VGL

GND

S+

5

4

1
2
3

6

J3

S-

S-

S-

TP1

TP2

SCL

SDA

4

1
2
3

J9

OTP_LDO

GND

4

1
2
3

J6

LS_CNTRL

GND

4

1
2
3

J5

LS_START

GND

4

1
2
3

J4

LN_CLK

GND

GND

GND

GND

GND

GND

GND

GND

1

2

3

J49

10

µ

F

C1

2.2

µ

F

C3

2.2

µ

F

C2

2.2

µ

F

C5

2.2

µ

F

C4

1

2

3

J48

CS1

CS2

CS

GVS

CS

GVS

1.00k

R2

1.00k

R1

1.00k

R3

GND

GND

GND

GND

GND

GND

GND

2.2

µ

F

C8

GND

GND

GND

1

2

3

J27

C

RC

1000pF

C26

1000pF

C25

GND

GND

6

4

5

S2

G12AP

1

2

3

J52

GND

VIN

LS_CNTRL_SW

LS_CNTRL_SW

1

2

J50

GCK9

GND

GND

GCK9

1

2

3

J25

C

RC

1000pF

C24

1000pF

C23

GND

GCK8

GND

GND

1

2

3

J23

C

RC

1000pF

C22

1000pF

C21

GND

GCK7

GND

GND

1

2

3

J29

C

RC

1000pF

C28

1000pF

C27

GND

GCK10

GND

GND

1

2

3

J31

C

RC

1000pF

C30

1000pF

C29

GND

GCK11

GND

GND

1

2

3

J33

C

RC

1000pF

C32

1000pF

C31

GND

GCK12

GND

GND

1

2

3

J35

C

RC

1000pF

C34

1000pF

C33

GND

GSP1

GND

GND

1

2

3

J11

C

R

C

100

R6

1000pF

C10

1000pF

C9

GND

G

C

K

1

G

N

D

GND

1

2

3

J13

C

R

C

1000pF

C12

1000pF

C11

GND

G

C

K

2

G

N

D

GND

1

2

3

J15

C

R

C

1000pF

C14

1000pF

C13

GND

G

C

K

3

G

N

D

GND

1

2

3

J17

C

R

C

1000pF

C16

1000pF

C15

GND

G

C

K

4

G

N

D

GND

1

2

3

J19

C

R

C

1000pF

C18

1000pF

C17

GND

G

C

K

5

G

N

D

GND

1

2

3

J21

C

R

C

1000pF

C20

1000pF

C19

GND

G

C

K

6

G

N

D

GND

GCK1

GCK2

GCK3

GCK4

GCK5

GCK6

GCK7

GCK8

GCK10

GCK11

GCK12

GSP1

1

2

3

J39

C

R

C

1000pF

C38

1000pF

C37

G

C

P

G

N

D

GND

GND

1

2

3

J41

C

R

C

1000pF

C40

1000pF

C39

G

P

P

1

G

N

D

GND

GND

1

2

3

J43

C

R

C

1000pF

C42

1000pF

C41

G

P

P

2

G

N

D

GND

GND

1

2

3

J45

C

R

C

1000pF

C44

1000pF

C43

V

S

S

G

N

D

GND

GND

1

2

3

J37

C

RC

1000pF

C36

1000pF

C35

GND

GSP2

GND

GND

GSP2

GCP

GGP1

GGP2

VSS

0.01

µ

F

C45

4

1

2

3

J12

4

1

2

3

J14

4

1

2

3

J16

4

1

2

3

J18

4

1

2

3

J20

4

1

2

3

J22

4

1

2

3

J24

4

1

2

3

J26

4

1

2

3

J28

4

1

2

3

J30

4

1

2

3

J32

4

1

2

3

J34

4

1

2

3

J36

4

1

2

3

J38

4

1

2

3

J40

4

1

2

3

J42

4

1

2

3

J44

4

1

2

3

J46

220

µ

F

C46

GND

220

µ

F

C47

GND

220

µ

F

C48

GND

VGL

VGH

VIN

10k

R24

10k

R25

VIN

1

2

J54

1

2

J55

1

2

J56

1

2

J57

1

2

J58

1

2

J59

1

2

J60

1

2

J61

1

2

J62

1

2

J63

1

2

J64

1

2

J65

0

R27

0

R26

GND

GND

G

C

K

1

G

C

K

2

G

C

K

3

G

C

K

4

G

C

K

5

G

C

K

6

G

C

K

7

G

C

K

8

G

C

K

9

G

C

K

1

0

G

C

K

1

1

G

C

K

1

2

100

R7

100

R8

100

R9

100

R10

100

R11

100

R12

100

R13

100

R14

100

R15

100

R16

100

R17

100

R18

100

R19

100

R20

100

R21

100

R22

100

R23

1000pF

C50

1000pF

C49

2.2

µ

F

C7

2.2

µ

F

C6

GND

GND

V

G

L

NC

1

NC

3

IN

4

OUT

5

2

GND

U2
TPS71533DCKRG4

0

R4

0.1

µ

F

C51

0.47

µ

F

C52

3V3

LDO

EXT_3V3

VIN

GND

EXT_3V3

3.3V

1
2
3

J7

EXT_3V3

1
2
3

J10

GND

3V3

I2C_SEL

GND

I2C_SEL

3.3V

SCL

1

SDA

2

LN_CLK

3

LS_CNTRL

4

LS_START

5

I2C_SEL

6

OTP_LDO

7

VIN

8

VGL1

9

GGP2

10

GGP1

11

VSS

12

GCP

13

GCK12

14

GCK11

15

GCK10

16

GCK9

17

GCK8

18

GCK7

19

CS2

20

CS1

21

GCK6

22

GCK5

23

GCK4

24

GCK3

25

GCK2

26

GCK1

27

GSP2

28

GSP1

29

VGH

30

GND

31

PLLC

32

PAD

33

TPS65680RSMR

U1

1

2

3

4

5

6

7

8

9

10

J53

     Copyright © 2017, Texas Instruments Incorporated      

www.ti.com

TPS65680 EVM Schematic

5

SLVUBB1 – November 2017

Submit Documentation Feedback

Copyright © 2017, Texas Instruments Incorporated

How to Use the TPS65680 Evaluation Module

ADVANCE INFORMATION

3

TPS65680 EVM Schematic

Figure 1

is for reference only; see the bill of materials in

Table 2

for specific values.

Figure 1. TPS65680 EVM Schematic

Summary of Contents for TPS65680

Page 1: ... outputs for generating start clear and reset and low frequency signals and panel discharge The evaluation module with its graphical user interface GUI enables the programming of the device from a Microsoft Windows 7 or 10 PC and provides easy access to all 18 outputs 3 supplies and logic inputs This user s guide describes the characteristics operation and use of the TPS65680 evaluation module EVM...

Page 2: ...nectors 8 5 Test Setup 8 5 1 EVM Operation 8 5 2 Software Setup to Change the Output Voltages and Configuration 9 5 3 Hardware Setup 9 5 4 Software Operation 9 6 TPS65680 EVM Assembly Drawings and Layout 11 7 Bill of Materials 14 List of Figures 1 TPS65680 EVM Schematic 5 2 Two and Four Terminal Connection 6 3 TPS65680 Software Window 10 4 TPS65680 EVM Top Composite 11 5 TPS65680 EVM Top Layer 12 ...

Page 3: ...ifter on an LCD TFT need to be synchronized to the timing controller that delivers the image content To keep TPS65680 synchronised to the timing controller signals just 2 digital input signals are necessary LN_CLK is the input signal for the TPS65680 internal PLL This fixed frequency signal is often set to the line frequency A rising edge on LS_START starts the programmed pattern from the programm...

Page 4: ...le sided two active layer printed circuit board PCB with all components on the top side 2 TPS65680 EVM Electrical and Performance Specifications Table 1 lists the EVM electrical and performance specifications Table 1 TPS65680 EVM Electrical and Performance Specifications Parameter Test Conditions MIN TYP MAX Unit Supply VI Operating input voltage on VIN pin 2 7 5 5 V V VGL Operating input voltage ...

Page 5: ...pF C43 V S S G ND GND GND 1 2 3 J37 C RC 1000pF C36 1000pF C35 GND GSP2 GND GND GSP2 GCP GGP1 GGP2 VSS 0 01 µF C45 4 1 2 3 J12 4 1 2 3 J14 4 1 2 3 J16 4 1 2 3 J18 4 1 2 3 J20 4 1 2 3 J22 4 1 2 3 J24 4 1 2 3 J26 4 1 2 3 J28 4 1 2 3 J30 4 1 2 3 J32 4 1 2 3 J34 4 1 2 3 J36 4 1 2 3 J38 4 1 2 3 J40 4 1 2 3 J42 4 1 2 3 J44 4 1 2 3 J46 220µF C46 GND 220µF C47 GND 220µF C48 GND VGL VGH VIN 10k R24 10k R25...

Page 6: ...ut Sense and GND Connector This header is the connection of the power supply V VGH and its sense connections The power supply must be connected between pins 1 and 2 VGH and pins 5 and 6 GND Twist the leads to the input supply and keep them as short as possible The input voltage must be between 9 V and 40 V 4 1 3 J3 VGL Input Sense and GND Connector This header is the connection of the power supply...

Page 7: ... from header J52 and set switch S2 to J52 4 3 Level Shifter Output Connectors 4 3 1 J36 J38 J12 J14 J16 J18 J20 J22 J24 J6 J28 J30 J32 J34 J40 J46 J42 and J44 GSP1 GSP2 GCK1 to GCK12 GCP VSS GGP1 and GGP2 Output and GND Connectors These headers are the connection of the 18 level shifter outputs Connect a scope probe between pins 1 and 2 GND and pins 3 and 4 output to measure this specific level sh...

Page 8: ...ith the TPS65680 on the EVM Pin 1 of J53 can drive LS_CNTRL via S2 pin 2 of J53 connects I2C_SEL to the GUI The GUI reads this voltage before any communication with the IC 4 4 4 J7 3 3V Voltage Limitation for USB2ANY The GUI is able to read the voltage on the I2C_SEL pin through pin 2 of J53 As USB2ANY allows a maximum voltage of 3 6 V on the pins of J53 it is necessary to limit the voltage on I2C...

Page 9: ...ke sure that the voltage delta from VGH to VGL never exceeds 55 V Connect the outputs of the frequency generator or microcontroller to J4 LN_CLLK and J5 LS_START Connect the 10 pin ribbon cable out of the HPA 665 bag to J53 the other end to the USB2ANY box and with the USB cable the other side of the USB2ANY box to the PC For the first startup set the switch S2 to SW for software and the two jumpe...

Page 10: ...up www ti com 10 SLVUBB1 November 2017 Submit Documentation Feedback Copyright 2017 Texas Instruments Incorporated How to Use the TPS65680 Evaluation Module ADVANCE INFORMATION Figure 3 TPS65680 Software Window ...

Page 11: ... Figure 4 through Figure 6 show the design of the TPS65680 EVM printed circuit board PCB The EVM has been designed using a two layer 35 μm 1 oz copper clad circuit board All components are on the top side and all active traces on the top and bottom layers allow you to easily view probe and evaluate the TPS65680 IC Moving components to both sides of the PCB can offer additional size reduction for s...

Page 12: ...rawings and Layout www ti com 12 SLVUBB1 November 2017 Submit Documentation Feedback Copyright 2017 Texas Instruments Incorporated How to Use the TPS65680 Evaluation Module ADVANCE INFORMATION Figure 5 TPS65680 EVM Top Layer ...

Page 13: ...ly Drawings and Layout 13 SLVUBB1 November 2017 Submit Documentation Feedback Copyright 2017 Texas Instruments Incorporated How to Use the TPS65680 Evaluation Module ADVANCE INFORMATION Figure 6 TPS65680 EVM Bottom Layer Bottom View ...

Page 14: ...M 1000 pF 16 V 10 X7R 0603 0603 GRM188R71C102KA01D Murata C45 1 0 01uF CAP CERM 0 01 µF 25 V 10 X7R 0402 0402 GCM155R71E103KA37D Murata C46 C47 C48 3 220uF CAP CERM 220 µF 6 3 V 20 X5R 1206_190 1206_190 GRM31CR60J227ME11L Murata C51 1 0 1uF CAP CERM 0 1 µF 10 V 10 X5R 0201 0201 CL03A104KP3NNNC Samsung C52 1 0 47uF CAP CERM 0 47 µF 10 V 10 X5R 0402 0402 GRM155R61A474KE15D Murata R1 R2 R3 3 1 00k RE...

Page 15: ...y set forth above or credit User s account for such EVM TI s liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warr...

Page 16: ...the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la réglementation d Industrie Canada le présent émetteur radio peut fo...

Page 17: ...ed loads Any loads applied outside of the specified output range may also result in unintended and or inaccurate operation and or possible permanent damage to the EVM and or interface electronics Please consult the EVM user guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even ...

Page 18: ...COST OF REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN TWELVE 12 MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS OCCURRED 8 2 Specif...

Page 19: ... TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI product...

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