Connector and Test Point Descriptions
4.1.15
J15: PB_IN, PB_OUT, POWER_ON, PGOOD, RESET/EN_EXTLDO, INT
J15, pin 1: PB_IN
J15 pin 1 is connected to PB_IN. Pulling PB_IN low starts up all dc-dc converters and LDOs according
to the internal power-up sequence. Refer to Table 9 in the data sheet (
) for information on the
internal power-up sequence. Note that if PB_IN is released high, all dc-dc converters and LDOs shut
down if the POWER_ON input is low. If POWER_ON is pulled high before PB_IN is released high
again, the dc-dc converters and LDOs remain on. Note that PB_IN is also connected to S1. PB_IN is
pulled up to AVDD6 with an internal 50-k
Ω
pull-up resistor. Pressing the Push-Button S1 pulls PB_IN
low.
J15, pin 2: PB_OUT
J15 pin 2 is connected to the open drain output PB_OUT. PB_OUT is driven by the status of PB_IN. If
PB_IN is low, PB_OUT is also low. If PB_IN is high, PB_OUT is driven to a high impedance state.
PB_OUT is pulled up to a pull-up voltage with resistor R37. In the factory default configuration, VSYS
is selected as the pull-up voltage. In addition, VOUT_DCDC1 and VOUT_DCDC2 can be configured as
pull-up voltages with R22 and R23, respectively.
J15, pin 3: POWER_ON
The POWER_ON pin must be pulled high before PB_IN is released high again to keep the dc-dc
converters and LDOs enabled once PB_IN is released high. Pulling POWER_ON low disables all dc-dc
converters and LDOs. POWER_ON is pulled up to a pull-up voltage with R32. In the factory default
configuration, VSYS is selected as the pull-up voltage. In addition, VOUT_DCDC1 and VOUT_DCDC2
can be configured as pull-up voltages with R22 and R23, respectively.
J15, pin 4: PGOOD
J15 pin 4 is connected to the open drain output PGOOD. PGOOD goes low depending on the setting
in the PGOODMASK register. In this register, different PGOOD bits of each dc-dc converter and LDO
can be connected to the PGOOD open drain output. PGOOD is connected to a pull-up voltage with
resistor R34. In the factory default EVM configuration, VSYS is selected as the pull-up voltage with
R21. In addition, VOUT_DCDC1 and VOUT_DCDC2 can be configured as pull-up voltages with R22
and R23, respectively.
J15, pin 6: RESET/EN_EXTLDO
J15 pin 5 is connected to the open drain output RESET. The TPS65070, TPS65073, TPS650731, and
TPS650732 each contain circuitry that can generate a reset pulse for a processor. The voltage at the
THRESHOLD pin is sensed; if this voltage goes above the threshold voltage of 1.0 V (typ), the RESET
output goes to a high impedance state after a delay time defined in the PGOOD register. If the voltage
at the THRESHOLD pin is below the threshold voltage, the PGOOD output is pulled low.
In the TPS65072, this pin is an active high push-pull output called EN_EXTLDO. This pin is controlled
internally and only used for sequencing the Sirf Prima or Atlas IV processors.
J15, pin 6: INT
J15 pin 6 is connected to the open drain output INT. The INT output indicates if there is an interrupt
active. The interrupts can be configured in the INT register. Different events can be masked as an
interrupt (for example, AC pin or USB pin power removed or applied), or as a touch screen Interface,
PB_IN.
INT is connected to a pull-up voltage with resistor R38. In the factory default EVM configuration, VSYS
is selected as the pull-up voltage with R21. In addition, VOUT_DCDC1 and VOUT_DCDC2 can be
configured as pull-up voltages with R22 and R23, respectively.
10
TPS6507xEVM
SLVU291B
–
April 2010
–
Revised September 2011
Copyright
©
2010
–
2011, Texas Instruments Incorporated