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1.2
Performance Specification
1.3
Modifications
2
Setup
2.1
Input / Output Connector Descriptions
Setup
provides a summary of the TPS62110EVM-101 performance specifications. All specifications are
given for an ambient temperature of 25
°
C.
Table 1. Performance Specification Summary
Specification
Test Conditions
Min
Typ
Max
Unit
Input Voltage
3.6
17
V
Output Voltage
Iout = 10 mA to 1500 mA
3.267
3.3
3.333
V
Output Current
0
1500
mA
Low Battery Output (LBO)
VIN
5.8
6.0
6.2
V
Power Good (PG)
VOUT
3.25
V
The PWB for this EVM is designed to accommodate both the fixed and adjustable versions of this IC. If
the fixed version is installed, replace R1 with a 0-
Ω
resistor; R1 and C3 are open. If additional filtering is
desired, C5 can be added.
1.3.1
Adjustable Output IC U1 Operation
U1 is configured for evaluation of the adjustable output version. This unit is configured for 3.3 V. Resistors
R1 and R2 are used to set the output voltage between 1.2 V and 16 V. See the TPS62110 datasheet
(SLVS585) for recommended values. The feedforward capacitor C3 may also need to be changed. For
more information see the data sheet.
1.3.2
Fixed Output Operation
U1 can be replaced with the fixed version for evaluation. For fixed-version operation, replace R1 with a
0-
Ω
resistor; R2 and C3 positions remain unpopulated.
This section describes how to properly use the TPS62110EVM-101.
J1–VIN
Positive input connection from the input supply for U1
J2–GND
Return connection from the input supply for U1, common with J4.
J3–VOUT
Output voltage connection
J4–GND
Output return connection, common with J2
J5–LBO/PG
Low battery output (LBO) pulled up to Vout; low indicates LBI is below its threshold.
Power good (PG), low indicates output voltage is less than 98.4% of the normal value.
JP1–SYNC
Input for synchronization to external clock signal. High forces low-noise PWM mode,
PFM/PWM
low enables power save PFM/PWM mode.
JP2–EN
Enable pin, low on the EN turns unit off.
TPS62110EVM-101
2
SLVU135 – June 2005