Texas Instruments TPS61130EVM User Manual Download Page 13

Setup

2-3

Setup

2.1.11 JP4 – LDOIN

This is the input connection to the integrated LDO of the TPS61130. Shorting
the VBAT pin and the center pin connects the VBAT input of the EVM to the
LDOIN on the TPS61130. Shorting the VOUT pin and the center pin connects
the VOUT pin of the EVM to the LDOIN on the TPS61130. This jumper may
be removed and any voltage up to 5.5 V can be applied to the input of the LDO
by directly connecting a voltage source to the center pin of JP4.

2.2

Setup

Connect an input supply between J1 and J2. The voltage range on this supply
should stay between 3.0 V and 5.5 V. Connect a load for the SEPIC converter
between J3 and J4. Connect a load for the LDO between J5 and J6. Configure
the SKIPEN jumper to the desired setting. Configure JP4 to provide power to
the LDO from the desired source.

2.3

Operation

The EVM has been optimized to operate from a Li-Ion battery input voltage
range (3.0 V to 4.2 V). The SEPIC output voltage is set to 3.3 V and is capable
of supplying 300 mA. The LDO output is set to 1.5 V and is capable of supplying
200 mA. After connecting the input and output connections, and setting the
SKIPEN jumper (JP1) to the desired setting, turn on the input supply, and then
enable the outputs as desired with JP2 and JP3.

The resistor divider on the LBI pin is designed to trip the LBO output when the
input supply voltage drops below 2.9 V.

Summary of Contents for TPS61130EVM

Page 1: ...TPS61130EVM May 2003 PMP Portable Power User s Guide SLVU086...

Page 2: ...t that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in wh...

Page 3: ...handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s r...

Page 4: ...ecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatur...

Page 5: ...The 3 3 V output is provided by the SEPIC converter and the 1 5 V output is provided by the integrated LDO This user s guide includes setup instructions a schematic diagram a bill of materials BOM an...

Page 6: ...the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in o...

Page 7: ...2 1 3 J3 VOUT 2 2 2 1 4 J4 GND 2 2 2 1 5 J5 LDOOUT 2 2 2 1 6 J6 GND 2 2 2 1 7 J7 PGOOD LBO 2 2 2 1 8 JP1 SKIPEN 2 2 2 1 9 JP2 EN 2 2 2 1 10 JP3 LDOEN 2 2 2 1 11 JP4 LDOIN 2 3 2 2 Setup 2 3 2 3 Operati...

Page 8: ...Contents viii 3 1 Top Layer 3 2 3 2 Bottom Layer 3 2 3 3 Top Assembly 3 3 4 1 TPS61130EVM 206 Schematic 4 2 4 1 TPS61130EVM 206 Bill of Materials 4 2...

Page 9: ...nd 1 5 V for the LDO output If desired this EVM can easily be modified to supply higher or lower output voltages The SEPIC converter can be set up to provide an output voltage between 2 5 V and 5 5 V...

Page 10: ...1 2...

Page 11: ...pter describes the jumpers and connectors on the EVM as well as how to properly connect setup and use the TPS61130EVM 206 Topic Page 2 1 Input Output Connector Descriptions 2 2 2 2 Setup 2 3 2 3 Opera...

Page 12: ...is the positive connection from the output of the LDO power supply Connect this pin to the positive input of the load 2 1 6 J6 GND This is the negative connection from the output of the LDO power supp...

Page 13: ...5 5 V Connect a load for the SEPIC converter between J3 and J4 Connect a load for the LDO between J5 and J6 Configure the SKIPEN jumper to the desired setting Configure JP4 to provide power to the LDO...

Page 14: ...2 4...

Page 15: ...3 1 Board Layout This chapter provides the TPS61130EVM 206 board layout and illustrations Topic Page 3 1 Layout 3 2 Chapter 3...

Page 16: ...e TPS61130EVM 206 PWB The nodes with high switching frequencies and currents are short and are isolated from the noise sensitive feedback circuitry Careful attention has been given to the rout ing of...

Page 17: ...Layout 3 3 Board Layout Figure 3 3 Top Assembly...

Page 18: ...3 4...

Page 19: ...4 1 Schematic and Bill of Materials This chapter provides the TPS61130EVM 206 schematic and bill of materials Topic Page 4 1 Schematic 4 2 4 2 Bill of Materials 4 2 Chapter 4...

Page 20: ...0 Murata GRM32ER61A226KA65 7 J1 J7 Header 2 pin 100 mil spacing 36 pin strip 0 100 In x 2 In Sullins PTC36SAAN 4 JP1 JP4 Header 3 pin 100 mil spacing 36 pin strip 0 100 In x 3 In Sullins PTC36SAAN 1 L...

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