Texas Instruments TPS562207EVM 2-A, User Manual, Page: 10 / 22

5 Board Layout
This section provides a description of the TPS562207EVM, board layout, and layer illustrations.
5.1 Layout
The board layout for the TPS562207EVM is shown in Figure 5-1 , Figure 5-2 and Figure 5-3 . The top layer
contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of
the TPS562207 and a large area filled with ground. Most of the signal traces are also located on the top side.
The input decoupling capacitors, C2, C3, and C4 are located as close to the IC as possible. The input and output
connectors, test points, and all of the components are located on the top side. The bottom layer is a ground
plane along with the switching node copper fill, signal ground copper fill and the feed back trace from the point of
regulation to the top of the resistor divider network. Both the top layer and bottom layer use 2 oz copper
thickness.
Figure 5-4 and Figure 5-5 are the TPS562207EVM top view and bottom view respectively.
Figure 5-1. TPS562207EVM Top Assembly
Board Layout www.ti.com
10 TPS562207EVM 2-A, Synchronous Step-down Converter Evaluation Module SLUUC43A – JANUARY 2020 – REVISED JULY 2020
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