Texas Instruments TPS55340EVM-017 User Manual Download Page 12

SW (20.0 V/div)

V

IN

 (5.00 V/div)

V

OUT

 (10.0 V/div)

Timebase (2.00 ms/div)

Board Layout

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12

SLVU668B – April 2012 – Revised July 2019

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Copyright © 2012–2019, Texas Instruments Incorporated

TPS55340EVM-017, 5-V to 12-V Input, 24-V Output Boost Evaluation Module

Figure 16

shows the shutdown waveforms for the EVM. The input voltage ramps down with the input

voltage power supply and EN is tied to V

IN

. When V

IN

is less than the 2.5-V typical UVLO, the converter

stops switching and the output voltage ramps down. The load is 120

Ω

.

Figure 16. TPS55340EVM-017 Power Down With V

IN

5

Board Layout

This section provides a description of the EVM board layout and layer illustrations.

5.1

Layout

The board layout for the EVM is shown in

Figure 17

through

Figure 21

The top-side layer of the EVM is

laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper.

The top layer contains the main power traces for V

IN

, V

OUT

, and SW. Also on the top layer are connections

for the remaining pins of the TPS55340 and a large area filled with ground. The internal layers and bottom
are primarily ground with additional fill areas for V

IN

and V

OUT

. The top-side ground traces connect to the

bottom and internal ground planes with multiple vias placed around the board. Nine vias directly under the
TPS55340 device provide a thermal path from the top-side ground plane to the bottom-side ground plane.

Place the output decoupling capacitors (C8–C11) as close to the IC as possible. The copper area of the
SW node is kept small minimizing noise. The vias near the diode, D1, on the V

OUT

plane aid with thermal

dissipation. Additionally, keep the voltage setpoint resistor divider components close to the IC. The voltage
divider network ties to the output voltage at the point of regulation, the copper V

OUT

trace at the J7 output

connector. For the TPS55340, an additional input bulk capacitor may be necessary, depending on the
EVM connection to the input supply. Critical analog circuits such as the voltage setpoint divider, frequency
set resistor, slow-start capacitor, and compensation components terminate to ground using a separate
ground trace on the top and bottom connected power ground, pour only at one point directly under the IC.

Summary of Contents for TPS55340EVM-017

Page 1: ...terials 15 List of Figures 1 TPS55340EVM 017 Efficiency 4 2 TPS55340EVM 017 Output Voltage Load Regulation 5 3 TPS55340EVM 017 Output Voltage Line Regulation 5 4 TPS55340EVM 017 VIN 5 V Transient Resp...

Page 2: ...imum Output Current TPS55340EVM 017 VIN 5 V to 12 V IOUTmax 800 mA VIN 5 V to 1 9 A VIN 12 V 2 Performance Specification Summary Table 2 provides a summary of the EVM performance specifications Specif...

Page 3: ...ons when changing the switching frequency input output voltage range input inductor output capacitors or compensation 4 Test Setup and Results This section describes how to properly connect set up and...

Page 4: ...point TP4 Output voltage test point at VOUT connector TP5 GND test point at VOUT connector 4 2 Efficiency The efficiency of this EVM peaks at a load current of about 300 mA at 5 V input and 800 mA at...

Page 5: ...ntation Feedback Copyright 2012 2019 Texas Instruments Incorporated TPS55340EVM 017 5 V to 12 V Input 24 V Output Boost Evaluation Module Figure 2 TPS55340EVM 017 Output Voltage Load Regulation Measur...

Page 6: ...55340EVM 017 5 V to 12 V Input 24 V Output Boost Evaluation Module 4 5 Load Transients Figure 4 and Figure 5 show the EVM s response to load transients The current step is from 25 to 75 of maximum rat...

Page 7: ...ted TPS55340EVM 017 5 V to 12 V Input 24 V Output Boost Evaluation Module 4 6 Loop Characteristics Figure 6 shows the EVM loop response characteristics Gain and phase plots are shown for VIN voltages...

Page 8: ...24 V Output Boost Evaluation Module Figure 8 shows the EVM output voltage ripple and inductor current ripple The output current is the rated full load of 1 9 A and VIN 12 V The ripple voltage is measu...

Page 9: ...Boost Evaluation Module 4 8 Pulse Skipping Operation The TPS55340 features pulse skipping for output regulation when operating at light loads Figure 9 shows the output voltage ripple and the pulse ski...

Page 10: ...EVM 017 5 V to 12 V Input 24 V Output Boost Evaluation Module Figure 12 shows the EVM input voltage ripple The output current is the rated full load of 1 9 A at VIN 12 V The ripple is measured directl...

Page 11: ...V Output Boost Evaluation Module Figure 14 shows the shutdown waveforms for the EVM The input voltage is 5V The EN goes low and the output voltage ramps from 24 V to VIN The load is 120 Figure 14 TPS5...

Page 12: ...pins of the TPS55340 and a large area filled with ground The internal layers and bottom are primarily ground with additional fill areas for VIN and VOUT The top side ground traces connect to the bott...

Page 13: ...sed July 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated TPS55340EVM 017 5 V to 12 V Input 24 V Output Boost Evaluation Module Figure 17 TPS55340EVM 017 Top Side...

Page 14: ...y 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated TPS55340EVM 017 5 V to 12 V Input 24 V Output Boost Evaluation Module Figure 19 TPS55340EVM 017 Internal Layer 1...

Page 15: ...SW 17 PWPD U1 TPS55340RTE C9 4 7uF C10 4 7uF C6 C2 10uF D1 TP5 VIN VIN SYNC SYNC www ti com Schematic and Bill of Materials 15 SLVU668B April 2012 Revised July 2019 Submit Documentation Feedback Copyr...

Page 16: ...or chip 1 16W 1 0603 STD STD 1 R2 10 0 k Resistor chip 1 16W 1 0603 STD 1 R3 2 55 k Resistor chip 1 16W 1 0603 STD 1 R4 78 7 k Resistor chip 1 16W 1 0603 STD 1 R5 49 9 Resistor chip 1 16W 1 0603 STD 1...

Page 17: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 18: ...the limits for a Class B digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This...

Page 19: ...o Technical Regulations of Radio Law of Japan User is required to follow the instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EV...

Page 20: ...rs or designees User assumes all responsibility and liability to ensure that any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and mea...

Page 21: ...M S AT ISSUE DURING THE PRIOR TWELVE 12 MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as...

Page 22: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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