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Introduction

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2

SLVUBO0A – March 2020 – Revised May 2020

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Copyright © 2020, Texas Instruments Incorporated

Using the TPS54JA20EVM-023 12-A, Buck Converter Evaluation Module

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TPS54JA20EVM Bottom-Side Layout

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List of Tables

1

Input Voltage and Output Current Summary

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TPS54JA20EVM Performance Specification Summary

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3

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TPS54JA20EVM Mode Pin Selection

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4

Enable Pin Selection

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TPS54JA20EVM EVM Connectors and Test Points

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TPS54JA20EVM List of Materials

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Trademarks

D-CAP3 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

1

Introduction

The TPS54JA20 is a D-CAP3™ synchronous buck converter designed for 12 A output current, and the
evaluation module is designed to demonstrate the small printed-circuit-board areas that may be achieved
when designing with the device. The high-side and low-side switching MOSFETs are integrated in the
device package along with their gate drive circuitry. Rated input voltage and output current ranges for the
evaluation module are given in

Table 1

.

1.1

Background

The EVM is setup to allow the user to evaluate the performance of the TPS54JA20 IC, and easily make
changes to multiple settings. The low drain-to-source on resistance of the MOSFETs allows the device to
achieve high efficiencies and keep the junction temperature low at high output currents. There is no need
for external compensation components since this device is designed with D-CAP3™ control topology. On
the EVM the switching frequency and the operation mode are externally selectable using a jumper to set
the resistor from the MODE pin to AGND. An external resistor divider allows for an adjustable output
voltage. Additionally, the device provides adjustable soft start, adjustable OC limit threshold, external
reference input, and an open-drain power good indicator. Lastly the TPS54JA20 device has a fixed
internal VIN under voltage lockout and externally adjustable UVLO using a resistor divider at the EN pin.

Table 1. Input Voltage and Output Current Summary

EVM

INPUT VOLTAGE RANGE

OUTPUT CURRENT

RANGE

TPS54JA20

V

IN

= 4 V to 16 V

0 A to 12 A

Figure 1. Safety Warnings

Summary of Contents for TPS548A28

Page 1: ...Efficiency 6 2 4 Load Regulation 8 2 5 Load Transients 9 2 6 Loop Characteristics 10 2 7 Output Voltage Ripple 11 2 8 Powering Up 12 3 Schematic List of Materials and Layout 13 3 1 Schematic 14 3 2 Li...

Page 2: ...ry Rated input voltage and output current ranges for the evaluation module are given in Table 1 1 1 Background The EVM is setup to allow the user to evaluate the performance of the TPS54JA20 IC and ea...

Page 3: ...16 V 0 12 12 A Internal LDO Voltage 3 0 V Line regulation VIN 4 V to 16 V IO 12 A 0 07 Load regulation VIN 12 V IO 0 A to 12 A 0 12 Load transient response IO 3 A to 9 A 2 A us Voltage change 50 mV Re...

Page 4: ...p Mode 121k 10 to AGND Short Pins 5 and 6 1000 kHz Forced CCM 60 4k 10 to AGND Short Pins 7 and 8 800 kHz Forced CCM 30 1k 10 to AGND Short Pins 9 and 10 600 kHz Forced CCM Short to AGND Short Pins 11...

Page 5: ...VOUT as the ground reference Table 5 TPS54JA20EVM EVM Connectors and Test Points REFERENCE DESIGNATOR FUNCTION J1 VIN input voltage connector see Table 1 for VIN range J2 PGND connection for input J3...

Page 6: ...S54JA20EVM 023 12 A Buck Converter Evaluation Module 2 3 Efficiency The efficiency of this EVM peaks at a load current of about 6 A and then decreases as the load current increases toward full load Th...

Page 7: ...80 90 100 Vout 2 5 V 800 kHz 800 nH VCC Int Skip D022 Vin 8 V Vin 12 V Vin 16 V www ti com Test Setup and Results 7 SLVUBO0A March 2020 Revised May 2020 Submit Documentation Feedback Copyright 2020 Te...

Page 8: ...2 511 2 514 2 517 800 kHz 800 nH FCCM VCC Int D024 Vin 8 V Vin 12 V Vin 16 V Test Setup and Results www ti com 8 SLVUBO0A March 2020 Revised May 2020 Submit Documentation Feedback Copyright 2020 Texa...

Page 9: ...Buck Converter Evaluation Module 2 5 Load Transients Figure 8 and Figure 9 show how the TPS54JA20EVM response to load transients The current step is from 25 to 75 Load The current step slew rate is 2...

Page 10: ...t 12 A D018 Gain Phase Test Setup and Results www ti com 10 SLVUBO0A March 2020 Revised May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Using the TPS54JA20EVM 023...

Page 11: ...23 12 A Buck Converter Evaluation Module 2 7 Output Voltage Ripple Figure 11 Figure 12 and Figure 13 show the TPS54JA20EVM output voltage ripple VIN 12 V The ripple voltage is measured directly across...

Page 12: ...rt up waveforms for the TPS54JA20EVM In Figure 14 the start up sequence begins as soon as the EN voltage is increased above the enable threshold voltage and the output voltage ramps up to the external...

Page 13: ...0 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Using the TPS54JA20EVM 023 12 A Buck Converter Evaluation Module 3 Schematic List of Materials and Layout This section pro...

Page 14: ...UBO0A March 2020 Revised May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Using the TPS54JA20EVM 023 12 A Buck Converter Evaluation Module 3 1 Schematic The followi...

Page 15: ...C80J476KE 18L MuRata C19 1 CAP CERM 0 22 uF 16 V 10 X7R 0603 C1608X7R1C224K08 0AC TDK C20 1 CAP CERM 0 022 uF 16 V 10 X7R 0603 C0603C223K4RACTU Kemet L1 1 Inductor Shielded Composite 800 nH 25 8 A 0 0...

Page 16: ...lane The internal layer 2 contains an additional large ground copper area as well as an additional VOUT copper fill The bottom layer is another ground plane with two additional traces for the output v...

Page 17: ...O0A March 2020 Revised May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Using the TPS54JA20EVM 023 12 A Buck Converter Evaluation Module Figure 16 TPS54JA20EVM Top...

Page 18: ...A March 2020 Revised May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Using the TPS54JA20EVM 023 12 A Buck Converter Evaluation Module Figure 18 TPS54JA20EVM Intern...

Page 19: ...dback Copyright 2020 Texas Instruments Incorporated Revision History Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from Original...

Page 20: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 21: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 22: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 23: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 24: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 25: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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