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Texas Instruments TPS546B24AEVM-2PH User Manual Download Page 6

3 Schematic

Figure 3-1

 through 

Figure 3-3

 illustrate the TPS546B24AEVM-2PH schematics.

SNS+

SMBALT
PM_CLK
PM_DAT

BC_CLK

BC_DAT

VIN

GND

SNS-

SW

VSH

SYNC

CNTL

S_VIN

EXT_5V

PG_S

P1
BSR104E1_Room.SchDoc

SNS+

SMBALT
PM_CLK
PM_DAT

BC_CLK

BC_DAT

VIN

GND

SNS-

SW

VSH

SYNC

CNTL

S_VIN

EXT_5V

PG_S

P2
BSR104E1_Room.SchDoc

1

2

3

4

5

6

7

8

9

10

J2

PMBus

GND

Green

2

1

LED1

1.00k

R28

CLK

CNTL

DATA

SMBALRT

47uF

C42

DNP

47uF

C38

DNP

47uF

C43

DNP

47uF

C44

DNP

47uF

C40

DNP

47uF

C39

DNP

47uF

C41

DNP

47uF

C35

220uF

C47

220uF

C48

47uF

C45

DNP

47uF

C30

47uF

C36

47uF

C37

DNP

GND

VOUT

47uF

C58

DNP

47uF

C54

47uF

C59

DNP

47uF

C60

DNP

47uF

C56

DNP

47uF

C55

47uF

C57

DNP

47uF

C51

220uF

C63

220uF

C64

47uF

C61

DNP

47uF

C62

47uF

C52

47uF

C53

GND

VOUT

49.9

R36

49.9

R35

Remote Sense N

47uF

C50

47uF

C49

0

R32

0

R33

0

R37

DNP

0

R39

DNP

VOUT

VSNS_P

VSNS_N

SW_P1

SW_P2

Remote Sense P

TP12

TP18

TP20

TP15

100uF

C34

100uF

C33

VSNS_P

VSNS_P

VSNS_N

VSNS_N

GND

TP17

1

2

T4

IN

1

IN

2

IN[CP]

3

CP

4

EN

5

GND[CP]

6

GND

7

FB

8

SET

9

OUT[FB]

10

OUT

11

OUT

12

DAP

13

U2

LP38798SD-ADJ

1µF

C22

10µF

C23

10nF

C24

47.5k

R29

15.0k

R30

560k

R31

GND

1
2

JP4

TP19

AVIN

Aux_5V

GND

Auxilary 5V_0A8 to Overide VDD5

GND

CHA1

CHB1

TP10

TP9

TP7

TP8

TP6

TP13

TP16

TP26

TP30

1

2

SMB2

TP22

TP25

1
2

JP3

TP27

TP29

TP31

TP23

TP21

Test Points for BCX

External SYNC Input

Test Points for VSHARE

TP32

GND

TP24

GND

EXT_SYNC

PG_Stack

BC_CLK

BC_DAT

SYNC

VSH

1
2

T1

1
2

T2

47uF

C25

47uF

C26

DNP

47uF

C27

DNP

47uF

C28

DNP

47uF

C29

47uF

C46

DNP

47uF

C65

DNP

47uF

C66

DNP

47uF

C67

DNP

47uF

C68

47uF

C69

DNP

47uF

C70

DNP

47uF

C31

47uF

C32

47uF

C71

DNP

47uF

C72

DNP

GND

GND

VOUT

TP11

49.9

R34

49.9

R38

TP14

TP28

Remote Sense N1

Remote Sense P1

VOUT

SMBALT
CLK
DATA
CNTL

SMBALT
CLK
DATA
CNTL

SMBALT

CLK

DATA

CNTL

T3

T5

1
3
5

6

4

2

7
9

10

8

12

11

J1

DNP

1
3
5

6

4

2

7
9

10

8

12

11

J3

DNP

VOUT

GND

GND

1

2

JP5

AVIN_LDO

1

2

JP6

DNP

AVIN

VBUS

1

D-

2

D+

3

ID

4

GND

5

6

7

8

1

1

1

0

9

J4

300nH

L2

300nH

L1

GND

1

2

JP8

DNP

VIN

Micro-USB Connection

VIN

TP33

DNP

30V

D2

30V

D1

HW1
BSR104E1_Hardware.SchDoc

Figure 3-1. TPS546B24AEVM-2PH Schematic Page 1

Schematic

www.ti.com

6

TPS546B24A 2-Phase SWIFT™ Step-Down Converter Evaluation Module User's Guide

SLUUC48A – FEBRUARY 2020 – REVISED FEBRUARY 2022

Submit Document Feedback

Copyright © 2022 Texas Instruments Incorporated

Summary of Contents for TPS546B24AEVM-2PH

Page 1: ...it Rail Input 13 4 7 Configuring EVM to Overdrive VDD5 13 5 EVM Configuration Using the Fusion GUI 14 5 1 Configuration Procedure 14 6 Test Procedure 14 6 1 Line and Load Regulation and Efficiency Mea...

Page 2: ...AEVM 2PH Top Side Component View Top View 25 Figure 8 4 TPS546B24AEVM 2PH Bottom Side Component View Bottom View 25 Figure 8 5 TPS546B24AEVM 2PH Top Copper Top View 26 Figure 8 6 TPS546B24AEVM 2PH Int...

Page 3: ...onse Measurements 16 Table 9 1 TPS546B24AEVM 2PH Bill of Materials 28 Trademarks All trademarks are the property of their respective owners www ti com Trademarks SLUUC48A FEBRUARY 2020 REVISED FEBRUAR...

Page 4: ...has signal traces components and component leads on the bottom of the board This may result in exposed voltages hot surfaces or sharp edges Do not reach under the board during operation CAUTION The ci...

Page 5: ...g threshold Set by default resistor divider JP2_P1 and JP2_P2 pins 3 and 4 shorted 4 75 V Output Characteristics Output voltage VOUT 0 8 V Output load current IOUT 0 40 A Output voltage regulation Lin...

Page 6: ...1 F C22 10 F C23 10nF C24 47 5k R29 15 0k R30 560k R31 GND 1 2 JP4 TP19 AVIN Aux_5V GND Auxilary 5V_0A8 to Overide VDD5 GND CHA1 CHB1 TP10 TP9 TP7 TP8 TP6 TP13 TP16 TP26 TP30 1 2 SMB2 TP22 TP25 1 2 JP...

Page 7: ...10 0k R8_P1 DNP AGND AGND 0 R17_P1 0 R24_P1 DNP GND 10 5k R10_P1 DNP MSEL2 10 5k R11_P1 DNP VSEL 10 5k R20_P1 DNP 10 5k R12_P1 DNP 53 6k R13_P1 DNP MSEL1 2 2 F C19_P1 DRTN 1 F C1_P1 GND DRTN 10 R2_P1...

Page 8: ...ND 10 0k R8_P2 AGND AGND 0 R17_P2 0 R24_P2 DNP GND 10 5k R10_P2 DNP MSEL2 10 5k R11_P2 DNP VSEL 10 5k R20_P2 DNP 10 5k R12_P2 DNP 53 6k R13_P2 DNP MSEL1 2 2 F C19_P2 DRTN 1 F C1_P2 GND DRTN 10 R2_P2 1...

Page 9: ...apable of supplying a minimum of 8 ADC to support 40 A load with 5 V input Connect input VIN and GND to T1 and T2 If the output voltage of the EVM is increased the power supply may need to be capable...

Page 10: ...TP3_P2 T H Loop GND_P2 GND pin voltage of U1_P2 device measurement point TP4_P1 T H Loop GND_P1 GND reference for switch node measurement of U1_P1 TP4_P2 T H Loop GND_P2 GND reference for switch node...

Page 11: ..._SEL2 U1_P1 and U1_P2 EN UVLO pin selections JP3 Header 100 mil 2 1 EN to GND Short to disable the auxiliary 5 V JP4 Header 100 mil 2 1 AVIN PVIN Short to connect to connect AVIN input to PVIN JP5 Hea...

Page 12: ...r EVM from a 5 V USB source T1 Terminal block 2 1 PVIN VIN connector T2 Terminal block 2 1 GND VIN connector T3 Terminal 90A Lug VOUT VOUT connector T4 Terminal block 2 1 Ext_AVIN External AVIN connec...

Page 13: ...pin from the PVIN pins 3 Apply the AVIN input to T4 4 V or greater AVIN is required to bring the VDD5 voltage high enough to enable conversion 4 If operation with 3 3 V PVIN is needed and the CNTL ju...

Page 14: ...the EVM See Section 4 2 for connections and test setup 3 Launch the Fusion GUI software See the screen shots in Section 10 for more information 4 Configure the EVM operating parameters as desired By...

Page 15: ...UT GND For more accurate efficiency measurements of the power train the voltage drop between the power train and the terminals should also be removed from the measurement Using the test points in Tabl...

Page 16: ...be limited to less than 30 mV TP17 CH_A Resulting output of VOUT Bode can be measured by a network analyzer with a CH_B CH_A configuration Measure the loop response with the following procedure 1 Set...

Page 17: ...6 V Figure 7 2 Efficiency VOUT Measured Using TP22 and TP25 7 2 Load and Line Regulation Measured Between TP22 and TP25 Output Current A Output Voltage V 0 5 10 15 20 25 30 35 40 0 795 0 796 0 797 0 7...

Page 18: ...y Hz Gain dB 1000 2000 5000 10000 100000 1000000 60 180 40 120 20 60 0 0 20 60 40 120 60 180 Gain Phase Figure 7 6 Bode Plot at 0 8 V Output at 12 VIN 20 A Load Performance Data and Typical Characteri...

Page 19: ...ipple With 0 A Load Figure 7 8 Output Ripple With 40 A Load www ti com Performance Data and Typical Characteristic Curves SLUUC48A FEBRUARY 2020 REVISED FEBRUARY 2022 Submit Document Feedback TPS546B2...

Page 20: ...he solder mask openings near the U1_P1 IC using a 1 GHz differential probe Figure 7 9 Low Side MOSFET VDS Figure 7 10 High Side MOSFET VDS Performance Data and Typical Characteristic Curves www ti com...

Page 21: ...rt Up From Control 0 A Load Figure 7 12 Start Up From Control 40 A CC Load www ti com Performance Data and Typical Characteristic Curves SLUUC48A FEBRUARY 2020 REVISED FEBRUARY 2022 Submit Document Fe...

Page 22: ...utdown From Control 0 A Load Figure 7 14 Shutdown From Control 20 A CC Load Performance Data and Typical Characteristic Curves www ti com 22 TPS546B24A 2 Phase SWIFT Step Down Converter Evaluation Mod...

Page 23: ...tween Two Phases Figure 7 16 illustrates the current sharing between two phases Figure 7 16 Inductor Current and Switch Node Waveform 40 A Load www ti com Performance Data and Typical Characteristic C...

Page 24: ...40 A Figure 7 17 Thermal Image Performance Data and Typical Characteristic Curves www ti com 24 TPS546B24A 2 Phase SWIFT Step Down Converter Evaluation Module User s Guide SLUUC48A FEBRUARY 2020 REVIS...

Page 25: ...EVM 2PH 3D Bottom View Figure 8 3 TPS546B24AEVM 2PH Top Side Component View Top View Figure 8 4 TPS546B24AEVM 2PH Bottom Side Component View Bottom View www ti com EVM Assembly Drawing and PCB Layout...

Page 26: ...2PH Internal Layer 2 Top View Figure 8 8 TPS546B24AEVM 2PH Internal Layer 3 Top View EVM Assembly Drawing and PCB Layout www ti com 26 TPS546B24A 2 Phase SWIFT Step Down Converter Evaluation Module U...

Page 27: ...M 2PH Internal Layer 6 Top View Figure 8 12 TPS546B24AEVM 2PH Internal Bottom Layer Top View www ti com EVM Assembly Drawing and PCB Layout SLUUC48A FEBRUARY 2020 REVISED FEBRUARY 2022 Submit Document...

Page 28: ...e 1 0603 0603 GCM188R72A103KA37J MuRata C25 C29 C30 C31 C32 C35 C36 C49 C50 C51 C52 C53 C54 C55 C62 C68 16 47 F CAP CERM 47 F 10 V 10 X7R 1210 1210 GRM32ER71A476KE15L MuRata C47 C48 C63 C64 4 220 F CA...

Page 29: ...200 Grade 0 0603 0603 CRCW060347K5FKEA Vishay Dale R30 1 15 0 k RES 15 0 k 1 0 1 W AEC Q200 Grade 0 0603 0603 CRCW060315K0FKEA Vishay Dale R31 1 560 k RES 560 k 1 0 1 W 0603 0603 RC0603FR 07560KL Yage...

Page 30: ...R24_P1 R24_P2 R37 R39 0 0 RES 0 5 0 1 W AEC Q200 Grade 0 0603 0603 ERJ 3GEY0R00V Panasonic R8_P1 0 10 0 k RES 10 0 k 1 0 1 W 0603 0603 RC0603FR 0710KL Yageo R10_P1 R10_P2 R11_P1 R11_P2 R12_P1 R12_P2 R...

Page 31: ...ower to be recognized by the Fusion GUI See Section 5 for the recommended procedure Figure 10 1 Select Device Scanning Mode www ti com Using the Fusion GUI SLUUC48A FEBRUARY 2020 REVISED FEBRUARY 2022...

Page 32: ...ges are committed to nonvolatile memory to store all the modifications in non volatile memory Both the loop controller device and the loop follower device are tied to same bus interface In a two phase...

Page 33: ...on and off power conversion By default the TPS546B24A is configured to CONTROL Pin Only This is the EN UVLO pin Figure 10 3 Configure ON_OFF_CONFIG www ti com Using the Fusion GUI SLUUC48A FEBRUARY 2...

Page 34: ...t Scale Loop To change these settings to a new value click on Stop Power Conversion then Close and continue The GUI will automatically disable conversion write the new value and enable conversion agai...

Page 35: ...SMBALERT Mask tab Figure 10 5 Figure 10 5 Configure SMBALERT Mask www ti com Using the Fusion GUI SLUUC48A FEBRUARY 2020 REVISED FEBRUARY 2022 Submit Document Feedback TPS546B24A 2 Phase SWIFT Step D...

Page 36: ...and Iout Cal Offset are found on the Device Info tab Figure 10 6 Figure 10 6 Configure Device Info Using the Fusion GUI www ti com 36 TPS546B24A 2 Phase SWIFT Step Down Converter Evaluation Module Us...

Page 37: ...OUT Temp of each phase Figure 10 7 Phase Commands www ti com Using the Fusion GUI SLUUC48A FEBRUARY 2020 REVISED FEBRUARY 2022 Submit Document Feedback TPS546B24A 2 Phase SWIFT Step Down Converter Eva...

Page 38: ...also shows other details like Hex encoding Figure 10 8 Configure All Config Using the Fusion GUI www ti com 38 TPS546B24A 2 Phase SWIFT Step Down Converter Evaluation Module User s Guide SLUUC48A FEB...

Page 39: ...wer up The EEPROM Value column shows the values currently configured to the related PMBus commands Figure 10 9 Configure Pin Strapping www ti com Using the Fusion GUI SLUUC48A FEBRUARY 2020 REVISED FE...

Page 40: ...g Control pin activation and OPERATION command Margin control Clear Fault Selecting Clear Faults clears any prior fault flags With two devices stacked together the Iout reading is the total load suppo...

Page 41: ...ision A February 2022 Page Updated the numbering format for tables figures and cross references throughout the document 4 Updated the user s guide title 4 Changed all instances of legacy terminology t...

Page 42: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 43: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 44: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 45: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 46: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 47: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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