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Layout
3-2
3.1
Layout
The board layout for the TPS54614 EVM, shown in Figure 3–1 through Figure
3–4, resembles a layer stack-up encountered in a typical application. The top
and bottom layers are 1.5 oz. copper, while the two internal layers are 0.5 oz.
copper. The circuit components are confined to a small area of the circuit
board. The two internal layers are identical and are used as quiet ground
planes. The power ground plane is routed on the top layer, and is tied to the
quiet (analog) ground planes at the output sense point (test point TP3). A wide
power ground plane is used to keep the input ground current from injecting
noise between the analog and power grounds. A total of 14 vias are used to
tie the thermal land area under the TPS54614 to the internal ground planes
and to the thermal plane on the back side of the board. The thermal plane on
the back side occupies only the area directly underneath the regulator
components, but should be made as large as possible in an actual application.
Figure 3–1. Top-Side Assembly
TPS5461x SWIFT Product Family
V
OUT
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
Adj
Part Number
TPS54611
TPS54612
TPS54613
TPS54614
TPS54615
TPS54616
TPS54610
TPS54614EVM
SLVP183
REV A
2001
Summary of Contents for TPS54614EVM 1.8-V SWIFT
Page 1: ...September 2001 PMP PD PS User s Guide SLVU053...
Page 6: ...vi...
Page 12: ...1 4...
Page 25: ...Layout 3 3 Board Layout Figure 3 2 Top Side Layout...
Page 26: ...Layout 3 4 Figure 3 3 Internal Layers Layout...
Page 27: ...Layout 3 5 Board Layout Figure 3 4 Bottom Side Layout...
Page 28: ...3 6...
Page 32: ...4 4...