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shows the loop characteristics for U2 with the 3 different ramp settings.

Frequency (Hz)

G

ai

n (

dB)

100 200

500 1000

10000

100000

1000000

-40

-20

0

20

40

60

Ramp = 4 pF
Ramp = 2 pF
Ramp = 1 pF

Figure 3-14. U2 Loop Gain with Different Ramp

Settings

Frequency (Hz)

Pha

se (

°)

100 200

500 1000

10000

100000

1000000

-120

-90

-60

-30

0

30

60

90

120

150

180

Ramp = 4 pF
Ramp = 2 pF
Ramp = 1 pF

Figure 3-15. U2 Loop Phase with Different Ramp

Settings

Test Setup and Results

16

TPS543620 SWIFT™ Step-Down Converter Evaluation Module User's Guide

SLVUBQ1A – AUGUST 2020 – REVISED MAY 2021

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Copyright © 2021 Texas Instruments Incorporated

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Summary of Contents for TPS543620

Page 1: ...e Ripple 18 3 7 Synchronizing to a Clock 19 3 8 Start up and Shutdown with EN 20 3 9 Start up and Shutdown with VIN 21 3 10 Start up Into Pre Bias 22 3 11 Hiccup Current Limit 23 3 12 Overvoltage Protection 24 3 13 Thermal Performance 25 4 Board Layout 26 4 1 Layout 26 5 Schematic and Bill of Materials 27 5 1 Schematic 28 5 2 Bill of Materials 30 6 Revision History 31 List of Figures Figure 3 6 U1...

Page 2: ...nd Recover 24 Figure 3 39 U1 Thermal Performance 6 A Load and U2 off 25 Figure 3 40 U2 Thermal Performance 6 A Load and U1 off 25 Figure 3 41 U1 Thermal Performance Both 6 A Load 25 Figure 3 42 U2 Thermal Performance Both 6 A Load 25 Figure 4 1 Top Side Composite View 26 Figure 4 2 Bottom Side Composite View Viewed From Bottom 26 Figure 4 3 Top Layer Layout 27 Figure 4 4 Mid Layer 1 Layout 27 Figu...

Page 3: ...n 100 mm2 The second design is designed to demonstrate the high efficiency that can be achieved when designing with the TPS543620 regulator The second design also includes jumpers that can be used to easily evaluate the features of the TPS543620 Table 1 1 Input Voltage and Output Current Summary EVM INPUT VOLTAGE RANGE OUTPUT CURRENT RANGE TPS543620EVM VIN 4 V to 18 V 0 A to 6 A 1 2 Before You Beg...

Page 4: ...005 V Output current range VIN 4 V to 13 2 V 0 6 A Line and load regulation VIN 4 V to 13 2 V IO 0 A to 6 A 0 1 Load transient response IO 1 5 A to 4 5 A Voltage change 25 mV Recovery time to within 0 5 70 µs IO 4 5 A to 1 5 A Voltage change 25 mV Recovery time to within 0 5 70 µs Loop bandwidth RO 0 2 Ω 201 kHz Phase margin 50 degrees Input ripple voltage IO 6 A 70 mVPP Output ripple voltage IO 6...

Page 5: ...IO 4 5 A to 1 5 A Voltage change 25 mV Recovery time to within 0 5 60 µs Loop bandwidth RO 0 2 Ω J18 short pins 3 and 4 140 kHz Phase margin 56 degrees Input ripple voltage IO 6 A 90 mVPP Output ripple voltage IO 6 A 6 mVPP Output rise time Set by MODE pin resistor All default J18 options 1 ms Current limit Set by MODE pin resistor J18 short pins 1 and 2 3 and 4 or 5 and 6 High Switching frequency...

Page 6: ... 1 After changing R7 the feedfoward capacitor C8 can also need to be changed OUT FBT FBB REF V R R 1 V u 1 In the U2 design there are a few ways to set the output voltage First jumper J14 can be used to select between the options shown in Table 2 1 If the desired output voltage is not available a resistor must be changed For output voltages less than 0 8 V TI recommends leaving J14 open and increa...

Page 7: ...e 2 3 If the desired option is not available change one of the resistors to the value which sets the desired option In the U1 design change the MODE resistor to the value which sets the desired option Table 2 3 MODE Selection JUMPER SETTING MODE RESISTOR CURRENT LIMIT SOFT START TIME RAMP 1 to 2 pin shorted 2 21 kΩ High 1 ms 1 pF 3 to 4 pin shorted 1 4 87 kΩ High 1 ms 2 pF 5 to 6 pin shorted 11 3 ...

Page 8: ...ed to J7 A pair of 20 AWG wires or better must be used for each connection With the maximum current limit setting the maximum load current capability is near 8 A before the TPS543620 goes into current limit Wire lengths must be minimized to reduce losses in the wires Test point TP11 provides a place to monitor the VIN input voltage with TP19 providing a convenient ground reference TP2 is used to m...

Page 9: ...header to connect enable divider to U2 Remove shunt to float EN pin of U2 to use internal UVLO to enable U2 J14 VOUT Select U2 VOUT selection header Use shunt to set output voltage See Table 2 1 J15 ENSYNC_U1 U1 2 pin header to connect U1 buffer output enable to ground Populate shunt to enable output of buffer Remove shunt to make buffer output high impedance J16 ENSYNC_U2 U2 2 pin header to conne...

Page 10: ...plot measurements TP23 EN_U2 U2 EN test point If you are applying an external voltage it must be kept below the absolute maximum voltage of the EN pin of 6 V TP24 VO_ADJ U2 Test point for injecting current into the FB divider to adjust the DC output voltage or inject a step to FB to test OVP TP25 VO_2NDSTG U2 Test point to measure output voltage after second stage filter if added to EVM TP26 SYNC ...

Page 11: ...ency of U2 Measuring the SW pin with this test point loads this node with 500 Ω and the efficiency measurement will include the power lost in this external resistance Remove the shunts from J11 and J13 as a small amount of power is dissipated in the EN resistor divider connected to U2 Table 3 3 Efficiency Measurement Test Points RELATED IC TEST POINT NAME REFERENCE DESIGNATOR FUNCTION U1 VIN_U1 TP...

Page 12: ... 65 70 75 80 85 90 95 100 VOUT 0 8 V VOUT 1 V VOUT 1 2 V VOUT 1 5 V VOUT 1 8 V VIN 12 V fSW 1000 kHz Figure 3 3 U2 Efficiency 1000 kHz Switching Frequency with Different Output Voltages Output Current A Efficiency 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 6 60 65 70 75 80 85 90 95 100 fSW 750 kHz fSW 1000 kHz fSW 1500 kHz fSW 2200 kHz VIN 9 V VOUT 1 V Figure 3 4 U2 Efficiency 1 V Output with Different S...

Page 13: ... VOUT 1 V RMODE 60 4 kΩ Figure 3 5 U2 Efficiency 1 V Output and Low Current Limit with Different Switching Frequencies www ti com Test Setup and Results SLVUBQ1A AUGUST 2020 REVISED MAY 2021 Submit Document Feedback TPS543620 SWIFT Step Down Converter Evaluation Module User s Guide 13 Copyright 2021 Texas Instruments Incorporated ...

Page 14: ...7 1 008 1 009 1 01 IOUT 0 A IOUT 3 A IOUT 6 A Figure 3 7 U1 Line Regulation Output Current A Output Voltage V 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 6 0 998 0 999 1 1 001 1 002 1 003 1 004 1 005 1 006 1 007 1 008 VIN 5 V VIN 12 V VIN 18 V Figure 3 8 U2 Load Regulation Input Voltage V Output Voltage V 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 998 0 999 1 1 001 1 002 1 003 1 004 1 005 1 006 1 007 1 008 ...

Page 15: ...is gain a 3 A step will result in 150 mV at the ISNS test point Note To use the load transient circuit with U1 move R27 to R28 Figure 3 12 and Figure 3 13 show the loop characteristics for both designs Gain and phase plots are shown for VIN voltage of 12 V and a 0 2 Ω resistive load Time 40 µs div IOUT 1 A div VOUT AC 20 mV div Figure 3 10 U1 Transient Response Time 100 µs div VOUT AC 20 mV div IO...

Page 16: ...p Gain with Different Ramp Settings Frequency Hz Phase 100 200 5001000 10000 100000 1000000 120 90 60 30 0 30 60 90 120 150 180 Ramp 4 pF Ramp 2 pF Ramp 1 pF Figure 3 15 U2 Loop Phase with Different Ramp Settings Test Setup and Results www ti com 16 TPS543620 SWIFT Step Down Converter Evaluation Module User s Guide SLVUBQ1A AUGUST 2020 REVISED MAY 2021 Submit Document Feedback Copyright 2021 Texas...

Page 17: ...tput Ripple No Load Time 1 µs div VOUT AC 10 mV div SW 5 V div Figure 3 17 U1 Output Ripple 6 A Load Time 1 µs div VOUT AC 10 mV div SW 5 V div Figure 3 18 U2 Output Ripple No Load Time 1 µs div VOUT AC 10 mV div SW 5 V div Figure 3 19 U2 Output Ripple 6 A Load www ti com Test Setup and Results SLVUBQ1A AUGUST 2020 REVISED MAY 2021 Submit Document Feedback TPS543620 SWIFT Step Down Converter Evalu...

Page 18: ...3 20 U1 Input Ripple No Load Time 1 µs div VIN AC 50 mV div SW 5 V div Figure 3 21 U1 Input Ripple 6 A Load Time 1 µs div VIN AC 10 mV div SW 5 V div Figure 3 22 U2 Input Ripple No Load Time 1 µs div VIN AC 50 mV div SW 5 V div Figure 3 23 U2 Input Ripple 6 A Load Test Setup and Results www ti com 18 TPS543620 SWIFT Step Down Converter Evaluation Module User s Guide SLVUBQ1A AUGUST 2020 REVISED MA...

Page 19: ...0 begins synchronizing to the clock After the clock goes away the TPS543620 switches at 70 of the internal clock frequency for four pulses then transitions back to the normal internal clock frequency There is only a small variation in the output voltage during these transitions Time 1 µs div SW_U1 5 V div SW_U2 5 V div SYNC 2 V div Figure 3 24 U1 and U2 Synchronized to a Clock Time 4 µs div VOUT A...

Page 20: ...and U2 respectively When the shunt is removed from ENOFF_U1 EN is released and the start up sequence begins for U1 When the shunt is placed on RDIV_VIN EN is pulled to the input voltage through the resistor divider and the start up sequence begins for U2 Time 400 µs div VOUT 500 mV div SW 10 V div EN 2 V div PGOOD 5 V div Figure 3 26 U2 Start up with EN No Load Time 400 µs div VOUT 500 mV div SW 1...

Page 21: ...tive UVLO threshold The rate at which VIN ramps down changes as soon as the TPS543620 is disabled because it is no longer loading the input supply Time 400 µs div VOUT 500 mV div VIN 10 V div EN 2 V div PGOOD 5 V div Figure 3 30 U2 Start up with VIN 0 3 Ω Load Time 1 ms div VOUT 500 mV div VIN 10 V div EN 2 V div PGOOD 5 V div Figure 3 31 U2 Shutdown with VIN 0 3 Ω Load www ti com Test Setup and R...

Page 22: ...utput voltage does not fully discharge before EN goes high again Time 400 µs div VOUT 500 mV div SW 10 V div EN 2 V div PGOOD 5 V div Figure 3 32 U2 Start up Into 0 5 V Pre Bias Test Setup and Results www ti com 22 TPS543620 SWIFT Step Down Converter Evaluation Module User s Guide SLVUBQ1A AUGUST 2020 REVISED MAY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 23: ...till present on the output In the next restart attempt the overload has been removed so the TPS543620 starts up normally Time 20 µs div SW 5 V div VOUT 500 mV div IL 5 A div Figure 3 33 U2 Output Overcurrent Protection Overload with High Limit Time 20 µs div VOUT 500 mV div SW 5 V div IL 2 A div Figure 3 34 U2 Output Overcurrent Protection Overload with Low Limit Time 10 µs div VOUT 500 mV div SW ...

Page 24: ...attempts to restart immediately after the OVP fault is cleared It does not wait for the hiccup time period Time 10 µs div VOUT 500 mV div SW 10 V div VOADJ 2 V div IL 5 A div Figure 3 37 U2 Overvoltage Protection Time 200 µs div VOUT 500 mV div SW 10 V div VOADJ 2 V div IL 5 A div Figure 3 38 U2 OVP and Recover Test Setup and Results www ti com 24 TPS543620 SWIFT Step Down Converter Evaluation Mod...

Page 25: ...soak time was used before taking each measurement Figure 3 39 U1 Thermal Performance 6 A Load and U2 off Figure 3 40 U2 Thermal Performance 6 A Load and U1 off Figure 3 41 U1 Thermal Performance Both 6 A Load Figure 3 42 U2 Thermal Performance Both 6 A Load www ti com Test Setup and Results SLVUBQ1A AUGUST 2020 REVISED MAY 2021 Submit Document Feedback TPS543620 SWIFT Step Down Converter Evaluatio...

Page 26: ...GND pins of the IC to help maximize the thermal performance Each TPS543620 circuit has its own dedicated ground are for quiet analog ground that is connected to the main power ground plane at a single point This single point connection is done using vias to the internal ground planes Lastly the voltage divider network ties to the output voltage at the point of regulation the copper VOUT area on th...

Page 27: ...chematic and Bill of Materials This section presents the TPS543620EVM schematic and bill of materials www ti com Schematic and Bill of Materials SLVUBQ1A AUGUST 2020 REVISED MAY 2021 Submit Document Feedback TPS543620 SWIFT Step Down Converter Evaluation Module User s Guide 27 Copyright 2021 Texas Instruments Incorporated ...

Page 28: ..._U1 PGND PGND 470nH L1 TP8 AGND_U1 VIN 0 R1 EN_U1 VIN_U1 PGOOD_U1 BP5_U1 Input 4 V to 18 V Output 1 0 V at 6 A TP5 PGND_EFF_U1 NT2 Net Tie VO_SNS_U1 VOUT_U1 0 R3 TP3 SW_U1 VIN 8 VIN 12 SW 10 SW 13 BOOT 14 BP5 6 EN 7 FB 4 MODE 2 PGOOD 3 SYNC FSEL 1 AGND 5 PGND 9 PGND 11 U1 4 1 2 SN74AHC1G125DCKR U3A GND 3 VCC 5 SN74AHC1G125DCKR U3B 0 1uF C10 SYNC BUFF_VCC BUFF_EN FSEL_U1 PGND BP5_U1 SW_U1 FB_U1 Fig...

Page 29: ...W 13 BOOT 14 BP5 6 EN 7 FB 4 MODE 2 PGOOD 3 SYNC FSEL 1 AGND 5 PGND 9 PGND 11 U2 MODE PGND FB AGND NT6 Net Tie PGND PGND PGND SW FB EN 2 2µF C28 AGND 10k R11 TP18 PGOOD_U2 FSEL TP21 BP5_U2 AGND 6 04k R17 16 9k R14 VIN TP20 AGND_U2 TP23 EN_U2 EN 0 R10 VIN_U2 150 mV 3 A LOAD TRANSIENT CIRCUIT 3W TP32 ISNS TP33 PGND To provide a 50 load step adjust high level of FGEN input until ISNS high level measu...

Page 30: ...Keystone J14 J17 J18 3 Header 2 54 mm 4x2 Gold TH Header 2 54mm 4x2 TH TSW 104 08 L D Samtec L1 1 470 nH Inductor Shielded Composite 470 nH 15 5 A 0 0041 Ω AEC Q200 Grade 1 SMD 4x4mm XEL4030 471MEB Coilcraft L2 1 Shielded Power Inductor SMD2 XEL5030 601MEC Coilcraft LBL1 1 Thermal Transfer Printable Labels 0 650 W x 0 200 H 10 000 per roll PCB Label 0 650 x 0 200 inch THT 14 423 10 Brady Q1 1 30 V...

Page 31: ...tone TP9 TP22 TP24 TP26 TP27 TP34 6 Test Point Multipurpose White TH White Multipurpose Testpoint 5012 Keystone TP10 TP28 TP29 3 Connector Receptacle 50 ohm TH SMB Connector SMBR004D00 JAE Electronics TP31 TP32 2 Test Point Multipurpose Yellow TH Yellow Multipurpose Testpoint 5014 Keystone U1 U2 2 TPS543620RPY RPY0014A VQFN 14 RPY0014A TPS543620RPY Texas Instruments U3 U4 2 Single Bus Buffer Gate ...

Page 32: ...ted the numbering format for tables figures and cross references throughout the document 3 Revision History www ti com 32 TPS543620 SWIFT Step Down Converter Evaluation Module User s Guide SLVUBQ1A AUGUST 2020 REVISED MAY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 33: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 34: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 35: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 36: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 37: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 38: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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