Texas Instruments TPS54336AEVM-010, User Manual, Page: 11 / 20

V = 2 V / div
OUT
Time = 2 msec / div
EN = 5 V / div
V = 20 V / div
IN
SS = 2 V / div
V = 2 V / div
OUT
Time = 2 msec / div
EN = 5 V / div
V = 20 V / div
IN
SS = 2 V / div
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Test Setup and Results
11 SLVUB77 – July 2017
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TPS54336AEVM-010 3-A Regulator Evaluation Module
2.10 Powering Down
Figure 13 and Figure 14 show the start-up waveforms for the TPS54336AEVM-010. In Figure 13 , the
output voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the
R1 and R2 resistor divider network. In
Figure 14 , the output is inhibited by using a jumper at JP1 to tie EN
to GND. The input voltage for these plots is 24 V and the load is 5 Ω .
Figure 13. TPS54336AEVM-010 Shut-down Relative to V
IN
Figure 14. TPS54336AEVM-010 Shut-down Relative to EN