Texas Instruments TPS54336AEVM-010 User Manual Download Page 4

Test Setup and Results

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SLVUB77 – July 2017

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TPS54336AEVM-010 3-A Regulator Evaluation Module

2

Test Setup and Results

This section describes how to properly connect, set up, and use the TPS54336AEVM-010 evaluation
module. The section also includes test results typical for the evaluation module and covers efficiency,
output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up.

2.1

Input/Output Connections

The TPS54336AEVM-010 is provided with input/output connectors and test points as shown in

Table 4

A

power supply capable of supplying 2 A must be connected to J1 through a pair of 20-AWG wires. The load
must be connected to J4 through a pair of 20-AWG wires. The maximum load current capability must be
at least 4 A to use the full capability of this EVM. Wire lengths must be minimized to reduce losses in the
wires. Test-point TP1 provides a place to monitor the V

IN

input voltages with TP2 providing a convenient

ground reference. TP6 is used to monitor the output voltage with TP7 as the ground reference.

Table 4. EVM Connectors and Test Points

Reference Designator

Function

J1

V

IN

(see

Table 1

for V

IN

range).

J2

V

OUT

, 5 V at 3 A maximum.

JP1

2-pin header for enable. Connect EN to ground to disable, open to enable.

TP1

V

IN

test point at V

IN

connector.

TP2

GND test point at V

IN

.

TP3

Slow start monitor test point for TPS54336A.

TP4

PH test point

TP5

Test point between voltage divider network and output. Used for loop response measurements.

TP6

Output voltage test point at OUT connector.

TP7

GND test point at OUT connector.

Summary of Contents for TPS54336AEVM-010

Page 1: ...n 6 4 TPS54336AEVM 010 Line Regulation 6 5 TPS54336AEVM 010 Transient Response 7 6 TPS54336AEVM 010 Loop Response 7 7 TPS54336AEVM 010 Output Ripple IOUT 3 A 8 8 TPS54336AEVM 010 Output Ripple IOUT 10...

Page 2: ...llows for an adjustable output voltage Additionally the TPS54336A provides adjustable slow start and undervoltage lockout inputs The absolute maximum input voltage is 30 V for the TPS54336AEVM 010 Tab...

Page 3: ...lculated using Equation 1 Use 100 k for R7 1 Table 3 lists the R9 and R10 values for some common output voltages Note that VIN must be in a range so that the minimum on time is greater than 145 ns and...

Page 4: ...he load must be connected to J4 through a pair of 20 AWG wires The maximum load current capability must be at least 4 A to use the full capability of this EVM Wire lengths must be minimized to reduce...

Page 5: ...ency The efficiency of this EVM peaks at a load current of about 0 5 A 1 A and then decreases as the load current increases towards full load Figure 1 shows the efficiency for the TPS54336AEVM 010 at...

Page 6: ...m 6 SLVUB77 July 2017 Submit Documentation Feedback Copyright 2017 Texas Instruments Incorporated TPS54336AEVM 010 3 A Regulator Evaluation Module 2 3 Output Voltage Load Regulation Figure 3 shows the...

Page 7: ...PS54336AEVM 010 3 A Regulator Evaluation Module 2 5 Load Transients Figure 5 shows the TPS54336AEVM 010 response to load transients The current step is from 25 to 75 of maximum rated load at 24 V inpu...

Page 8: ...struments Incorporated TPS54336AEVM 010 3 A Regulator Evaluation Module 2 7 Output Voltage Ripple Figure 7 Figure 8 and Figure 9 show the TPS54336AEVM 010 output voltage ripple for full load light loa...

Page 9: ...opyright 2017 Texas Instruments Incorporated TPS54336AEVM 010 3 A Regulator Evaluation Module Figure 9 TPS54336AEVM 010 Output Ripple IOUT 0 A 2 8 Input Voltage Ripple Figure 10 shows the TPS54336AEVM...

Page 10: ...the output voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1and R2 resistor divider network In Figure 12 the input voltage is initially applied and the output...

Page 11: ...Module 2 10 Powering Down Figure 13 and Figure 14 show the start up waveforms for the TPS54336AEVM 010 In Figure 13 the output voltage ramps down as soon as the input voltage falls below the UVLO sto...

Page 12: ...capacitor The bottom layer contains a ground plane plus a copper fill area for VPHASE an etch run to connect the upper resistor of the voltage set point divider to the regulation point at the J2 outpu...

Page 13: ...VUB77 July 2017 Submit Documentation Feedback Copyright 2017 Texas Instruments Incorporated TPS54336AEVM 010 3 A Regulator Evaluation Module Figure 16 TPS54336AEVM 010 Top Side Layout Figure 17 TPS543...

Page 14: ...DAR open VIN 8V 28V VOUT 5V 3A MAX 0 01 F Copyright 2017 Texas Instruments Incorporated Schematic and Bill of Materials www ti com 14 SLVUB77 July 2017 Submit Documentation Feedback Copyright 2017 Tex...

Page 15: ...mil 2x1 Gold plated 230 mil above insulator 2x1 100mil TSW 102 07 G S Samtec Inc L1 1 15uH Inductor Shielded Composite 15uH 5 8A 0 04 ohm SMD 322x158x322mil IHLP3232DZER150M5A Vishay Dale R1 1 220k RE...

Page 16: ...set forth above or credit User s account for such EVM TI s liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that...

Page 17: ...the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain great...

Page 18: ...t the EVM user guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even with the...

Page 19: ...OST OF REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF...

Page 20: ...TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD...

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