Texas Instruments TPS54334EVM-722, User Manual, Page: 12 / 21

Board Layout
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3 Board Layout
This section provides a description of the TPS54334EVM-722, board layout, and layer illustrations.
3.1 Layout
Figure 15 through Figure 17 show the board layout for the TPS54334EVM-722. The topside layer of the
EVM is laid out in a manner typical of a user application. The top and bottom layers are 2-oz. copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and VPHASE. Also on the top layer are
connections for the remaining pins of the TPS54334 and a large area filled with ground. To facilitate the
placement of the main input bypass capacitor as close to the V
IN
and GND pins as possible, the trace for
VPHASE is routed to the bottom layer immediately at the pin 3 connection. It is routed back to the top
layer at the L1 inductor and C3 BOOT capacitor. The bottom layer contains a ground plane plus a copper
fill area for VPHASE, an etch run to connect the upper resistor of the voltage set point divider to the
regulation point at the J2 output connector, and a trace to connect the upper resistor of the UVLO set
point divider network to V
IN
. The top-side ground areas are connected to the bottom and internal ground
planes with multiple vias placed around the board including four vias directly under the TPS54334 device
to provide a thermal path from the top-side ground area to the bottom-side and internal ground planes.
The input decoupling capacitors (C2, and C1) and bootstrap capacitor (C3) are all located as close to the
IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC.
For the TPS54334, an additional input bulk capacitor may be required, depending on the EVM connection
to the input supply.
Figure 15. TPS54334EVM-722 Top-Side Assembly
12 TPS54334EVM-722 3-A Regulator Evaluation Module SLVUAH4 – August 2015
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