Texas Instruments TPS54202EVM-716, User Manual

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Test Setup and Results
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12 SLVUAP3 – April 2016
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TPS54202EVM-716 2-A Regulator Evaluation Module
2.9 Powering Down
Figure 13 and Figure 14 show the start-up waveforms for the TPS54202EVM-716. In Figure 13 , the output
voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the R4
and R5 resistor divider network. In
Figure 14 , the output is inhibited by using a 3.3-V logic signal between
EN and GND. The input voltage for these plots is 24 V and the load is 5 Ω .
Figure 13. TPS54202EVM-716 Shutdown Relative to V
IN
Figure 14. TPS54202EVM-716 Shutdown Relative to EN