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Page 1: ...E December 2003 PMP Systems Power User s Guide SLVU102...
Page 2: ...itute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual p...
Page 3: ...handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s r...
Page 4: ...ere is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 55 C The EVM is designe...
Page 5: ...out Chapter 4 Schematic and Bill of Materials FCC Warning This equipment is intended for use in a laboratory test environment only It gen erates uses and can radiate radio frequency energy and has not...
Page 6: ...4 2 Test Setup and Results 2 1 2 1 Input Output Connections 2 2 2 2 Efficiency 2 3 2 3 Power Dissipation 2 4 2 4 Output Voltage Regulation 2 5 2 5 Load Transients 2 6 2 6 Loop Characteristic 2 7 2 7 O...
Page 7: ...Measured Loop Response TPS54110 VI 6 V 2 7 2 9 Measured Output Voltage Ripple TPS54110 2 8 2 10 Input Voltage Ripple TPS54110 2 8 2 11 Powering Up 2 9 3 1 Top Side Layout 3 2 3 2 Bottom Side Layout 3...
Page 8: ...th support documentation for the TPS54110EVM 044 evaluation module HPA044 The TPS54110EVM 044 performance specifications are provided along with a schematic and bill of material Topic Page 1 1 Backgro...
Page 9: ...ctor The high side and low side MOSFETs are incorporated inside the TPS54110 package allowing for compact designs with minimal external circuitry The low drain to source on resistance of the internal...
Page 10: ...Units Input voltage range 3 0 3 3 or 5 0 6 0 V Output voltage set point 1 5 V Output current range VI 3 V to 5 5 V 1 5 1 5 A Line regulation IO 0 1 5 A VI 3 V to 6 V 0 02 Load regulation VI 3 3 V IO 0...
Page 11: ...ot available with VI less than 4 V Equation 1 1 R2 10 kW 0 891 V V O 0 891 V Table 1 3 Output Voltage Programming Output Voltage V R2 Value 1 2 28 7 k 1 5 14 7 k 1 8 9 76 k 2 5 5 49 k 3 3 3 74 k The m...
Page 12: ...044 and covers efficiency output voltage regulation load transients loop response output ripple input ripple and startup Topic Page 2 1 Input Output Connections 2 2 2 2 Efficiency 2 3 2 3 Power Dissip...
Page 13: ...a place to easily connect an oscilloscope voltage probe to monitor the output voltage The TPS54110 is intended to be used as a point of load regulator In typical applications it is usually located clo...
Page 14: ...emperature of 25_C The efficiency is lower at higher ambient temperatures due to temperature variation in the drain to source resistance of the MOSFETs The efficiency is slightly lower at 700 kHz than...
Page 15: ...nction temperature is approximately 60 C wheras the case temperature is approximately 55 C The total circuit losses at 25 C are shown in Figure 2 3 Power dissipation is shown for input voltages of 3 3...
Page 16: ...re given for an ambient temperature of 25 C Figure 2 4 Load Regulation 0 1 0 02 0 04 0 0 02 0 04 0 1 0 0 25 0 5 0 75 1 1 25 1 5 OUTPUT VOLTAGE vs OUTPUT CURRENT IO Output Current A Output Voltage Chan...
Page 17: ...oad transients is shown in Figure 2 6 The current step is from 25 to 75 of maximum rated load Total peak to peak voltage variation is as shown including ripple and noise on the output Figure 2 6 Load...
Page 18: ...e Figure 2 7 Measured Loop Response TPS54110 VI 3 V 60 50 40 30 20 10 0 10 20 30 40 50 60 100 1 k 10 k 100 k 1 M 180 150 120 90 60 30 0 30 60 90 120 150 180 Phase Gain Gain dB f Frequency Hz MEASURED...
Page 19: ...red directly across output capacitors Figure 2 9 Measured Output Voltage Ripple TPS54110 VO AC 20 mV div Vphase 5 V div t Time 500 ns div 2 8 Input Voltage Ripple The TPS54110EVM 044 input voltage rip...
Page 20: ...ernally set rate until the final output set point is reached The output voltage waveforms during power up do not depend on load currents Longer delay and ramp times can be programmed using an external...
Page 21: ...2 10...
Page 22: ...3 1 Board Layout This chapter provides a description of the TPS54110EVM 044 board layout and layer illustrations Topic Page 3 1 Layout 3 2 Chapter 3...
Page 23: ...layer are connections for the remaining pins of the TPS54110 and a large area filled with ground The bottom layer contains ground and VO copper areas and some signal routing The top and bottom ground...
Page 24: ...Layout 3 3 Board Layout Figure 3 2 Bottom Side Layout Figure 3 3 Top Side Assembly...
Page 25: ...4 1 Schematic and Bill of Materials The TPS54110EVM 044 schematic and bill of materials are presented in this chapter Topic Page 4 1 Schematic 4 2 4 2 Bill of Materials 4 3 Chapter 4...
Page 26: ...C4 C9 0 1 F 10 F R4 71 5 k R7 10 k TP6 VIN U1 TPS54110PWP RT SYNC SS ENA VBIAS VIN VIN VIN PGND PGND PGND PwrPd PH PH PH BOOT PH PH AGND VSENSE COMP PWRGD 20 19 18 17 16 15 14 13 12 11 21 1 2 3 4 5 6...
Page 27: ...chip 10 k 1 16 W 1 402 std std 1 R2 Resistor chip 14 7 k 1 16 W x 402 std std 1 R3 Resistor chip 1 74 k 1 16 W x 402 std std 1 R4 Resistor chip 71 5 k 1 16 W 1 402 std std 1 R5 Resistor chip 432 1 16...
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