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General Configurations
5
SLVUBN7A – April 2019 – Revised August 2019
Copyright © 2019, Texas Instruments Incorporated
TPS2596EVM: Evaluation Module for TPS2596xx
Table 2. Input and Output Connector Functionality
Connector
Label
Description
J1
CH1
VIN1(+), GND(–)
CH1 Input power supply to the EVM
J2
VOUT1(+),GND(–)
CH1 Output power from the EVM
J9
CH2
VIN2(+), GND(–)
CH2 Input power supply to the EVM
J10
VOUT2(+),GND(–)
CH2 Output power from the EVM
describes the test point availability.
Table 3. Test Points Description
Channel
Test Points
Label
Description
CH1
TP1
VIN1
CH1 Input power supply to the EVM
TP3
EN1
CH1 Active high enable and under voltage input
TP6
OVP1
CH1 OVCSEL pin voltage
TP5
ILIM1
CH1 Current monitor. Load current
≈
V
ILIM1
/ (647 µA/A × R
ILIM1
)
TP7
DVDT1
CH1 DVDT pin voltage
TP2
VOUT1
CH1 Output from the EVM
TP4
FLTb1
CH1 Fault test point
TP8, TP12
GND
GND
TP11, TP13
GND
GND
TP23
SGND1
CH1 Signal GND
CH2
TP17
VIN2
CH2 Input power supply to the EVM
TP19
EN2
CH2 Active high enable and under voltage input
TP22
OVP2
CH2 OVLO pin voltage
TP21
ILIM2
CH2 Current monitor. Load current
≈
V
ILIM2
/ (647 µA/A × R
ILIM2
)
TP16
DVDT2
CH2 DVDT pin voltage
TP18
VOUT2
CH2 Output from the EVM
TP20
FLTb2
CH2 Fault test point
TP9, TP14
GND
GND
TP15, TP10
GND
GND
TP24
SGND1
CH2 Signal GND