EVM Assembly Drawings and Layout Guidelines
8
SLVUB94 – October 2017
Copyright © 2017, Texas Instruments Incorporated
TPS254900AQ1EVM-003 Evaluation Module
5.2
Layout Guidelines
Use the following layout guidelines:
•
TPS254900A-Q1 placement:
Place the TPS254900A-Q1 near the USB output connector and OUT pin
filter capacitors. Connect the exposed pad to the GND pin and the system ground plane using an array
of vias.
•
IN pin bypass capacitance: Place the 0.1-
μ
F bypass capacitor near the IN pin and make the
connection using a low inductance trace.
•
DP-OUT, DM-OUT and DP-IN, DM-IN traces:
Route these traces as controlled impedance differential
pairs per the USB-2.0 specification. Minimize the use of vias in the high-speed data lines.
provides a good signal routing example for the high-speed data traces. In this example, the data pairs
are routed as edge-coupled microstrips with nominal differential impedance of 90
Ω
. The reference
plane is tied to GND and is shown in
. Ensure that the reference plane is void of cuts or splits
above the differential pairs to prevent impedance discontinuities.
•
ILIM_LO and ILIM_HI pin connections:
Current-limit, set-point accuracy can be compromised by
stray current leakage from a higher voltage source to the ILIM_LO or ILIM_HI pins. Ensure that there is
adequate spacing between IN pin copper/trace and ILIM_LO pin trace to prevent contaminant buildup
during the PCB assembly process.
•
The capacitor on BIAS helps improve IEC ESD performance, a 2.2-µF capacitor should be placed
close to BIAS and the whole “current” path from BIAS to GND across this capacitor should be as short
as possible. Do not use a via along the connection traces.
•
A 10-µF output capacitor should be placed close to the OUT pin and TVS.
5.3
EMI Containment
EMI containment methods are shown in the following list:
•
Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives)
•
Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching
nodes (minimize exposed radiating surface).
•
Use copper ground planes (possible stitching) and top-layer copper floods (surround circuitry with
ground floods)
•
Use a 4-layer PCB, if economically feasible (for better grounding)
•
Minimize the amount of copper area associated with input traces (to minimize radiated pickup)
•
Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads as
boundary line)
•
Possible use of common-mode inductors
