Texas Instruments TPS23882B1EVM, User Manual, Page: 21 / 31

5.2 Layout Guidelines
5.2.1 Supply Voltage Decoupling
Provide power supply pin bypass to the TPS23882B1 device as follows:
• 0.1 µF, 100 V, X7R ceramic at pin 28 (VPWR)
• 0.1 µF, 50 V, X7R ceramic at pin 1 (VDD)
5.2.2 Port Current Kelvin Sensing
KSENSA is shared between SEN1 and SEN2, while KSENSB is shared between SEN3 and SEN4. In order to
optimize the accuracy of the measurement, the PCB layout must be done carefully to minimize the impact of
PCB trace resistance. Refer to
Figure 5-10 as an example.
5.2.3 Ground Plane Spacing and Isolation (GND, GND1, and EARTH nets)
Appropriate spacing should be provided between the GND, GND1, and EARTH nets as shown in Figure 5-6 .
5.3 PCB Drawings
Figure 5-4 through Figure 5-12 show the PCB layouts and assemblies for this EVM.
Figure 5-4. BOOST-PSEMTHR8-097 (Motherboard) Top Side Assembly
www.ti.com EVM Schematic, Layout Guidelines, PCB Assembly and Layer Plots
SLVUC36 – APRIL 2021
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TPS23882B1EVM: PoE, PSE, TPS23882B1
Evaluation Module
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