Texas Instruments TPS23758EVM-080, User Manual, Page: 14 / 27

7.2 Layout Guidelines
The layout of the PoE front end should follow power and EMI or ESD best-practice guidelines. A basic set of
recommendations includes:
• Pin 22 of the TPS23758 is omitted from the IC to ensure high voltage clearance from Pin 24 (DRAIN).
Therefore, the Pin 22 footprint should be removed when laying out the TPS23758.
• It is recommended having at least 8 vias (VSS) connecting the exposed thermal pad through a top layer
plane (2 oz copper recommended) to a bottom VSS plane (2 oz. copper recommended) to help with thermal
dissipation.
• The Pin 24 of the TPS23758 should be near the power transformer and the current sense resistor should be
close to Pin 1 of the TPS23758to minimize the primary loop.
• Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode
bridges, TVS and 0.1-μF capacitor, and TPS23758 converter input bulk capacitor.
• Make all leads as short as possible with wide power traces and paired signal and return.
• No crossovers of signals from one part of the flow to another are allowed.
• Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage
rails and between the input and an isolated converter output.
• Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay copper
fills in the power path.
The DC-to-DC converter layout benefits from basic rules such as:
• Having at least 4 vias (VDD) near the power transformer pin connected to VDD through multiple layer planes
to help with thermal dissipation of the power transformer.
• Having at least 6 vias (secondary ground) near the power transformer pin connected to secondary ground
through multiple layer planes to help with thermal dissipation of the power transformer.
• Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses, which include
the power semiconductors and magnetics.
• Minimize the trace length of high current power semiconductors and magnetic components.
• Use the ground plane for the switching currents carefully.
• Keep the high-current and high-voltage switching away from low-level sensing circuits including those outside
the power supply.
• Proper spacing around the high-voltage sections of the converter.
EVM Assembly Drawings and Layout Guidelines www.ti.com
14 TPS23758EVM-080 Evaluation Module SLVUBO2B – APRIL 2019 – REVISED DECEMBER 2020
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