Schematic
5
SLVUBC9 – December 2017
Copyright © 2017, Texas Instruments Incorporated
TPS23523EVM-863 Evaluation Module
2
Schematic
illustrates the EVM schematic.
Figure 3. TPS23523EVM-863 Schematic
3
General Configuration and Description
3.1
Physical Access
lists the TPS23523EVM connector and functionality,
describes the test point availability,
and
describes the default jumper configuration.
Table 2. Connector Functionality
Connector
Label
Description
J1, J2
RTN
Power bus input – tie the high side of the power-supply inputs and outputs
here.
J3
Overvoltage jumper – shorts OV to GND disabling OV.
J4
Neg48V
Neg48V input – tie the low side of the input supply here.
J5
Vout_FLTD
Output bus – low-side output after EMI inductor.
J6
VEE_PWR
Tie Extra loads here to test advanced configuration.
J7
Jumper selects current monitoring between R20 and R21.
J8
Jumper selects current monitoring between R20 and R21.
J9
Connector for the INA dongle.