Texas Instruments TPL1401, User Manual

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4.1 BOOSTXL-DAC-PORT Schematic
Figure 4-1 and Figure 4-2 illustrate the BOOSTXL-DAC-PORT schematic.
3V3 5V
GND
3V3
25V
0.1uF
C6
GND
25V
0.1uF
C11
GND
GND
VIO
MOSI_CLR
33 R27
33 R28
33 R25
33 R26 CS0_A1
SPI2C_USBBTC_RST
33 R32 LDAC
33 R6
33 R5
33 R4
MISO_LDAC_RSTSEL
SCL_USBBTC_RSTSEL_LDAC
SDA_CLR_RSTSEL_LDAC
GND
GND GND
33 R11
SCLK_A0
33 R45
33 R39
33 R12
33 R13
33 R41
1
2
3
4
5
J12
393570005
VCC VSS EXT_VDD EXT_VIO
GND
16V
10uF
C13
16V
10uF
C12
50V
10uF
C15
50V
10uF
C14
GND GND GND GND
VDD
EXT_VDD
5V
TP1
VDD
VIO
EXT_VIO
3V3
TP3
VIO
33 R42
VDD
1.0k
R7
GND
VIO
1.0k
R9
GND
33 R40
33 R44
0 R38
0 R43
BO_MISO_LDAC_RSTSEL
BO_SCLK_A0
BO_MOSI_CLR
BO_CS0_A1
BO_SPI2C_USBBTC_RST
BO_SDA_CLR_RSTSEL_LDAC
D2 CDBU0245
D1 CDBU0245
4.99k
R8
4.99k
R10
VDD Selection
VIO Selection
External Power Supply Interface
Launchpad Interface
Launchpad Interface
Push-pull IO Level Translator
External Power Supply Detection
BO_LDAC
1 2 3
J8
EXT_LDAC
EXT_LDAC
33 R35
LDAC Low Jitter Path Selection
TP5
LDAC
VCCA
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
GND
11
GND
12
GND
13
B8
14
B7
15
B6
16
B5
17
B4
18
B3
19
B2
20
B1
21
OE
22
VCCB
23
VCCB
24
SN74LVC8T245PW
U2
GND
25V
0.1uF
C7
GND
10.0k
R37
GND
VREF_A
1
A1
2
A2
3
A3
4
A4
5
NC
6
GND
7
EN
8
NC
9
B4
10
B3
11
B2
12
B1
13
VREF_B
14
LSF0204DPWR
U1
25V
0.1uF
C3
GND
VIO
BO_SCL_USBBTC_RSTSEL_LDAC
3V3
25V
0.1uF
C5
GND
33 R20
33 R19
33 R18
MISO_LDAC_RSTSEL
SCL_USBBTC_RSTSEL_LDAC
SDA_CLR_RSTSEL_LDAC
GND
10.0k
R23
10.0k
R3
10.0k
R2
10.0k
R1
3V3
GND
VIO
DAC_VIO
TP4
DAC_VIO
10.0k
R24
10.0k
R22
3V3 3V3
DAC_VIO
33 R21
33 R17
1
2
3
J10
1
2
3
J9 0 R15
0 R14
SCL_USBBTC_RSTSEL_LDAC
SDA_CLR_RSTSEL_LDAC
BO_SCL_USBBTC_RSTSEL_LDAC
BO_SDA_CLR_RSTSEL_LDAC
10.0k R29
SPI_BUF_EN SPI_BUF_EN
1 2
J11
BO_SCL_USBBTC_RSTSEL_LDAC
BO_SDA_CLR_RSTSEL_LDAC
10uF
10V
C1
10uF
10V
C2
1
3
5
6
4
2
7
9
10
8
12 11
14 13
16 15
18 17
20 19
J14
1
3
5
6
4
2
7
9
10
8
12 11
14 13
16 15
18 17
20 19
J13
ESQ-110-14-T-D
By default, DAC_VIO is OFF. However, the VIO is
ON to make sure EEPROM is read. The VIO is by
default connected to 3V3 and then based on the
EEPROM reading, it is switch to the right value.
This assumes that the BO board has another buffer
to isolate the EEPROM signals from the DAC
unless DAC_VIO is present
EXT_VDD-max = 5.5V
EXT_VIO-max = 3.6V
VCC-max = 43V
VSS-max = -21.5V
(VCC-VSS)-max = 43V
This jumper provides a clean
option to supply low-jitter
LDAC for high-THD
applications. When external
LDAC is not going through
level translator, VIO must be at
3V3
This circuit is mainly intended to
check whether VDD and VIO
are in the recommended range or
not.
For MSP430G2, the position of
MOSI and MISO are
interchanged. Hence, the resistor
options are provided
The EXT_LDAC is supplied to
the uC for SPI or I2C trigger. It
is also supplied to the DAC.
When EXT_LDAC is not
present, a timer is used to
generate a synchronous LDAC
Figure 4-1. BOOSTXL-DAC-PORT Schematic Page 1
Schematic, PCB Layout, and Bill of Materials www.ti.com
22 TPL1401 Evaluation Module SNAU257 – OCTOBER 2020
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