3.6 EVM Power Tree
The TPA3223EVM includes a few options for power configuration so that various input types can be evaluated.
3.6.1 TPA3223 Supplies
The TPA3223 device has a few power supplies which each have their own voltage range and rules. Details for
each supply are as shown:
•
PVDD
– This is the main device supply which accepts from 10 V to 45 V. Power output of the device is
derived solely from PVDD and therefore it is important to configure this supply according to the chosen output
configuration and load. Complete details are included in the TPA3223 datasheet.
•
VDD
– This supply is used for the non-PVDD power of the device for blocks such as the front-end and control
circuitry. VDD is powered by 5 V directly and tied to GVDD and AVDD pins.
•
GVDD
and
AVDD
– These pins are used for the gate drive and analog supply of the device. GVDD and
AVDD accept only 5 V which can be provided through the TP or the 5V through J24.
Table 3-5. Power Supply Summary
PVDD (V)
VDD (V)
AVDD (V)
GVDD (V)
10.0 to 45.0
5.0
5.0 (Tied to VDD)
5.0 (Tied to VDD)
3.6.2 TPA3223EVM Power Options
TPA3223 requires that 5 V is provided externally to VDD, AVDD, and GVDD. The major input configurations are
listed in the following sections by the supplies available.
3.6.2.1 PVDD Only (12 V to 45 V)
This power mode is the default setup when the board is tested and shipped. The user can connect any valid
supply voltage to J1 and the onboard LDOs will generate the required non-PVDD voltages. PVDD itself always
connects directly to the TPA3223 PVDD pins. Setup for this mode is the same as described in
.
3.6.2.2 PVDD (12 V to 45 V) and One Non-5-V Supply
This power mode is useful for certain applications where a system has one higher voltage used for PVDD and
a second lower voltage that may be used for device pullups and other supplies (VDD, GVDD, and AVDD). The
PVDD voltage can still be connected to J1 but jumpers J29 and J26 must be removed.
In the case of the TPA3223EVM, only 12V can be accepted as a non-5-V Supply and should be connected to pin
2 of J26 (12V).
3.6.2.3 PVDD (12 V to 45 V) and 5-V Supply
This power mode is most useful for systems in which a 5-V supply is already available due to additional circuitry
like an MCU or wireless module. On the EVM, this method is also the preferred way to measure efficiency of
the TPA3223 device. The PVDD voltage can still be connected to J1 but jumper J29 must be removed. The 5-V
supply must be connected to TP40.
The same 5-V input is used for the TPA3223 supplies (AVDD, VDD, and GVDD), the EVM reset control (U7), all
TPA3223 device pullups (RESET, HEAD, FREQ_ADJ, FAULT, OTW_CLIP), and status LEDs D4 and D2.
The 5-V supply can be isolated by by disconnecting J24. Once J24 jumper is removed, 5 V can be fed to only
the TPA3223 supplies through Pin 2 on the jumper and all other 5 V are being powered through 5 V LDO.
Either approach can be used to measure efficiency, but the most accurate numbers will be with the 5-V supply
separated so the TPA3223 supply voltage is isolated and measured independently of board LEDs, reset control,
and so forth.
3.7 LC Response and Overview
Included near the output of the TPA3223 device are four output LC filters. These output filters filter the PWM
output leaving only the audio content at high power which is fed to the speakers. The board uses a Sagami
10-µH inductor and 1-µF film capacitor to form this LC filter. Using the equations listed in
LC Filter Design
), the filter low pass cut-off is as follows:
Hardware Configuration
12
TPA3223 Evaluation Module
SLAU874 – OCTOBER 2022
Copyright © 2022 Texas Instruments Incorporated