if RTICPUCy
0,
≠
if RTIUDCPy = 0,
t
COMPx
t
RTICLK
x (RT 1) x RTIUDCPy
=
t
COMPx
t x
RTICLK
x RTIUDCPy
=
t
COMPx
t
RTICLK
x (RT 1) x 2
32
=
(2 +1)
32
Module Operation
587
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Real-Time Interrupt (RTI) Module
17.2.1.1 Counter and Capture Read Consistency
Portions of the device internal databus are 32-bits wide. If the application wants to read the 64-bit counters
or the 64-bit capture values, a certain order of 32-bit read operations needs to be followed. This is to
prevent one counter incrementing in between the two separate read operations to both counters.
Reading the Counters
The free running counter (RTIFRCx) must be read first. This priority will ensure that in the cycle when the
CPU reads RTIFRCx, the up counter value is stored in its counter register (RTIUCx). The second read has
to access the up counter register (RTIUCx), which then holds the value which corresponds to the number
of RTICLK cycles that have elapsed at the time reading the free running counter register (RTIFRCx).
NOTE:
The up counters are implemented as shadow registers. Reading RTIUCx without having
read RTIFRCx first will return always the same value. RTIUCx will only be updated when
RTIFRCx is read.
Reading the Capture Values
The free running counter capture register (RTICAFRCx) must be read first. This priority will ensure that in
the cycle when the CPU reads RTICAFRCx, the up counter value is stored in its counter register
(RTICAUCx). The second read has to access the up counter register (RTICAUCx), which then holds the
value captured at the time when reading the capture free running counter register (RTICAFRCx).
NOTE:
The capture up counter registers are implemented as shadow registers. Reading RTICAUCx
without having read RTICAFRCx first will return always the same value. RTICAUCx will only
be updated when RTICAFRCx is read.
17.2.1.2 Capture Feature
Both counter blocks also provide a capture feature on external events. Two capture sources can trigger
the capture event. The source triggering the block is configurable (RTICAPCTRL). The sources originate
from the Vectored Interrupt Manager (VIM) and allow the generation of capture events when a peripheral
modules has generated an interrupt. Any of the peripheral interrupts can be selected as the capture event
in the VIM.
When an event is detected, RTIUCx and RTIFRCx are stored in the capture up counter (RTICAUCx) and
capture free running counter (RTICAFRCx) registers. The read order of the captured values must be the
same as the read order of the actual counters (see
17.2.2 Interrupt/DMA Requests
There are four compare registers (RTICOMPy) to generate interrupt requests to the VIM or DMA requests
to the DMA controller. The interrupts can be used to generate different timebases for the operating
system. Each of the compare registers can be configured to be compared to either RTIFRC0 or RTIFRC1.
When the counter value matches the compare value, an interrupt is generated. To allow periodic
interrupts, a certain value can be added to the compare value in RTICOMPy automatically. This value is
stored in the update compare register (RTIUDCPy) and will be added after a compare is matched. The
period of the generated interrupt/DMA request can be calculated with:
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