ESM Control Registers
570
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Error Signaling Module (ESM)
16.4.9 ESM Status Register 3 (ESMSR3)
This register is dedicated for Group3.
Figure 16-19. ESM Status Register 3 (ESMSR3) [offset = 20h]
31
16
ESF3[31:0]
R/W1CP-X/0
15
0
ESF3[15:0]
R/W1CP-X/0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -
n
= value after reset/PORRST;
X
= value is unchanged
Table 16-11. ESM Status Register 3 (ESMSR3) Field Descriptions
Bit
Field
Value
Description
31-0
ESF3
Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.
0
Read: No error occurred.
Write: Leaves the bit unchanged.
1
Read: Error occurred.
Write: Clears the bit.
16.4.10 ESM ERROR Pin Status Register (ESMEPSR)
Figure 16-20. ESM ERROR Pin Status Register (ESMEPSR) [offset = 24h]
31
16
Reserved
R-0
15
1
0
Reserved
EPSF
R-0
R-X/1
LEGEND: R = Read only; -
n
= value after reset/PORRST;
X
= value is unchanged
Table 16-12. ESM ERROR Pin Status Register (ESMEPSR) Field Descriptions
Bit
Field
Value
Description
31-1
Reserved
0
Reads return 0. Writes have no effect.
0
EPSF
ERROR Pin Status Flag. Provides status information for the ERROR Pin.
Read/Write in User and Privileged mode.
0
Read: ERROR pin is low (active) if any error has occurred.
Write: Writes have no effect.
1
Read: ERROR pin is high if no error has occurred.
Write: Writes have no effect.
Note:
This flag will be set to 1 after PORRST. The value will be unchanged after RST. The ERROR
pin status remains unchanged during after RST.