Control of Special Multiplexed Options
314
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
I/O Multiplexing and Control Module (IOMM)
6.5.1 Control of SDRAM Clock (EMIF_CLK)
As shown in
, PINMMR9[0] is set by default. This blocks the EMIF SDRAM clock signal
(EMIF_CLK) from being output from the microcontroller. If the EMIF is used to connect to an external
SDRAM module, then the application must enable the SDRAM clock output by clearing the PINMMR9[0]
bit and set the PINMMR9[1].
6.5.2 Control for other EMIF Outputs
There are some EMIF signals (EMIF_ADDR[00], EMIF_ADDR[01], EMIF_ADDR[06], EMIF_ADDR[07],
EMIF_ADDR[08], EMIF_BA[1], EMIF_nCS[0], EMIF_nCS[3]), that are multiplexed with N2HET2 signals.
For applications that require the use of these N2HET2 signals, it is inconvenient if the EMIF starts driving
these address and control signals as output after reset is released and before the application can
configure the I/O Multiplexing Module registers. Therefore, these EMIF signals are blocked from being
output by default when PINMMR174[8]=1 and PINMMR174[9]=0. In this condition, these EMIF/N2HET2
terminals are configured as inputs and pulled down. An application that requires the EMIF functionality
must set PINMMR174[8]=0 and PINMMR174[9]=1. This causes the EMIF address and control signals to
then be output on the EMIF/N2HET2 terminals when the EMIF functionality is selected via the IOMM
output multiplexing control registers.
6.5.3 Control of Ethernet Controller Mode
PINMMR160[24] is set by default. This bit is used to enable the RMII (Reduced Media Independent
Interface of the Ethernet controller). If the application desires to use the MII (Media Independent Interface
of the Ethernet controller), then the PINMMR160[24] must be cleared.
6.5.4 Control of ADC Trigger Events
The microcontrollers contain two Analog-to-Digital Converter modules: ADC1 and ADC2. The ADC
conversions can be started using a rising or falling or both edges as the trigger event. Both the ADC
modules support up to eight event trigger inputs. There are two sets of these 8 inputs for each ADC. The
option for each of these 8 inputs are controlled by registers in the I/O multiplexing module as shown in
and
.
Table 6-4. ADC1 Trigger Event Selection
Group Source
Select, G1SRC,
G2SRC or EVSRC
Event #
PINMMR161[0]
PINMMR161[1]
Control Option A
Control Option B
Trigger Source
000
1
x
x
NA
NA
AD1EVT
001
2
1
0
PINMMR161[8] = x
PINMMR161[9] = x
N2HET1[8]
0
1
PINMMR161[8] = 1
PINMMR161[9] = 0
N2HET2[5]
0
1
PINMMR161[8] = 0
PINMMR161[9] = 1
ePWM_B
010
3
1
0
NA
NA
N2HET1[10]
0
1
NA
NA
N2HET1[27]
011
4
1
0
PINMMR161[16] = x
PINMMR161[17] = x
RTI1 Comp0
0
1
PINMMR161[16] = 1
PINMMR161[17] = 0
RTI1 Comp0
0
1
PINMMR161[16] = 0
PINMMR161[17] = 1
ePWM_A1
100
5
1
0
NA
NA
N2HET1[12]
0
1
NA
NA
N2HET1[17]
101
6
1
0
PINMMR161[24] = x
PINMMR161[25] = x
N2HET1[14]
0
1
PINMMR161[24] = 1
PINMMR161[25] = 0
N2HET1[19]
0
1
PINMMR161[24] = 0
PINMMR161[25] = 1
N2HET2[1]
110
7
1
0
PINMMR162[0] = x
PINMMR162[1] = x
GIOB[0]
0
1
PINMMR162[0] = 1
PINMMR162[1] = 0
N2HET1[11]
0
1
PINMMR162[0] = 0
PINMMR162[1] = 1
ePWM_A2
111
8
1
0
PINMMR162[8] = x
PINMMR162[9] = x
GIOB[1]
0
1
PINMMR162[8] = 1
PINMMR162[9] = 0
N2HET2[13]
0
1
PINMMR162[8] = 0
PINMMR162[9] = 1
ePWM_AB
