How to Use SCM
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SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
SCR Control Module (SCM)
3.2.3.1
Control Key to invert Parity Polarity for Interconnect Hardware Checker Parity Detection
Diagnostic
The interconnect receives parity bits associated with input control and address signals and does the parity
checking. The interconnect also generates parity bits for corresponding control and address signals. To
test the parity checking logic, the SCM can invert the parity polarity bit to the interconnect to purposely
creates a fail or pass parity checking condition.
has recommendations on how you should test the parity detection logic inside interconnect
hardware checker.
3.2.3.2
Global Error Clearing Control Key
Interconnect subsystem triggers global error in case of any of the following errors happen:
•
Parity checking error on any bus master.
•
Arbitration error.
•
Protocol conversion error.
•
Self-test fail in self-test diagnostic mode.
A global error from interconnect subsystem can result in non-recoverable condition for the device. It is
recommended that user issues a global error clear by writing 0xA to the GLOBAL_ERR_CLR of the
SCMCNTRL register in conjunction to system reset.
3.2.3.3
Interconnect Hardware Checker Self-test
Interconnect hardware checker performs four major diagnostic checks on interconnect:
•
Arbitration
•
Timeout
•
Protocol conversion
•
Parity on control / address signals
Thus, it is necessary to be able to do self-test of interconnect hardware checker logic whenever you
decide at appropriate time in the application control loop. The self-test logic will create normal and
erroneous transaction from each master to each slave according to the bus connection matrix to verify that
the hardware checker properly functioning. See
for detail on how to start self-test.
3.3
How to Use SCM
3.3.1 How to Check the Parity Compare Logic
Interconnect has associated parity bits for control and address bit of the communication bus. Parity check
is done for all control and address input. Parity generation is done for all control and address output.
For fail safety reason, parity checking logic needs to be tested at your choice of time in their control loop.
To enable the parity detection test, you should switch to privilege mode and write 0xA to
SCMCNTRL[27:24] control register. This will invert the parity polarity and testing for only one cycle. The
SCM module will reset the control key back to 0x5 once it triggers an inversion parity polarity to
interconnect hardware checker. Since parity polarity is inverted only inside interconnect, the interconnect
will flag parity error for input control and address signals. The interconnect also output an inverted polarity
for output control and address signals. Thus, master and slave IP connected to interconnect could
potentially generate parity error as well. This way, the corresponding parity detection logic in master and
slave IP can be tested at the same time. You should clear all parity error status bits residing in master IP,
slave IP, or interconnect status registers.
Note that the hardware only does parity inversion check in one cycle so that it does not block out CPU
access to Flash and RAM on subsequence cycle.
