Module Operation
1248
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
FlexRay Module
26.2.10 Receive Process
26.2.10.1 Dedicated Receive Buffers
A portion of the Communication Controller message buffers can be configured as dedicated receive
buffers by programming bit CFG in the header section of the corresponding message buffer to 0. This can
be done through the Write Header Section 1 register.
The following possibilities exist to assign a receive buffer to the Communication Controller channels:
•
Static segment:
–
channel A or channel B
–
channel A and channel B (the communication controller stores the first semantically valid frame)
•
Dynamic segment:
–
channel A or channel B
The communication controller transfers payload data of valid received messages from the shift registers of
the FlexRay protocol controller (channel A or B) to the receive buffer with the matching filter configuration.
A receive buffer stores all frame elements except the frame CRC.
All message buffers configured for reception in static or dynamic segment are reconfigurable during
runtime depending on the configuration of MRC.SEC(1-0) of the Message RAM Configuration register. If a
message buffer is reconfigured (header section updated) during runtime it may happen that in the
currently active communication cycle a received message is lost.
If two or more receive buffers meet the filter criteria simultaneously, the receive buffer with the lowest
message buffer number is updated with the received message.
26.2.10.2 Frame Reception
The following steps are required to prepare a dedicated message buffer for reception:
•
Configure the receive buffer in the Message RAM through WRHS1, WRHS2, and WRHS3
•
Transfer the configuration from input buffer to the message RAM by writing the number of the target
message buffer to the Input Buffer Command Request (IBCR) register.
Once these steps are performed, the message buffer functions as an active receive buffer and participates
in the internal acceptance filtering process, which takes place every time the communication controller
receives a message. The first matching receive buffer is updated from the received message.
If a valid payload segment was stored in the data section of a message buffer, the corresponding ND flag
in the NDAT1,2,3,4 registers is set, and, if bit MBI in the header section of that message buffer is set, flag
SIR.RXI in the Status Interrupt Register is set to 1. If enabled, an interrupt is generated.
In case that bit ND was already set when the Message Handler updates the message buffer, bit
MBS.MLST of the corresponding message buffer is set and the unprocessed message data is lost.
If no frame, a null frame, or a corrupted frame is received in a slot, the data section of the message buffer
configured for this slot is not updated. In this case only the flags in the corresponding message buffer
status (MBS) is updated.
When the Message Handler changes the message buffer status MBS in the header section of a message
buffer, the corresponding MBC flag in the Message Buffer Status Changed 1,2,3 or 4 register is set, and if
bit MBI in the header section of that message buffer is set, flag SIR.MBSI in the Status Interrupt Register
is set to 1. If enabled an interrupt is generated.
If the payload length of a received frame PLR(6-0) is longer than the value programmed by PLC(6-0) in
the header section of the corresponding message buffer, the data field stored in the message buffer is
truncated to that length.
NOTE:
The ND and MBS flags are automatically cleared by the message handler when the payload
data and the header of a received message have been transferred to the output buffer,
respectively.
