Control Registers and RAM
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
67
Bits 23:21
Reserved
Bits 20:16
T2CDELAY.
Transmit-end-to-chip-select-inactive-delay.
T2CDELAY is used in master mode only. It defines a hold time for the slave
device that delays the chip select deactivation by a multiple of ICLK cycles
after the last bit is transferred. T2CDELAY can be configured between 1 and
32 ICLK cycles.
Figure 16.
Example: t
T2CDELAY
= 4 ICLK cycles
The hold time value is calculated as shown in Equation 2..
Equation 2.
Transmit-End-to-Chip-Select-Inactive-Delay-
Time
Example: ICLK = 25 MHz; T2CDELAY = 02h;
> t
T2CDELAY
= 120 ns;
After the last data bit (or parity bit) is being transferred the chip
select signal is held active for 120 ns.
Bits 15:8
T2EDELAY.
Transmit-data-finished-to-ENA-pin-inactive-time-out.
T2EDELAY is used in master mode only. It defines a time-out value as a
multiple of SPI clock before the ENAble signal has to become inactive and
after the CS becomes inactive. The SPI clock depends on which data format
is selected. If the slave device is missing one or more clock edges, it’s
becoming de-synchronized (see Section 7.20). Although the master has
finished the data transfer the slave is still waiting for the missed clock pulses
and the ENA signal isn’t disabled. The T2EDELAY defines a time-out value
that triggers the DESYNC flag, if the ENA signal isn’t deactivated in time.
SCS
CLK
SOMI
t
T2CDELAY
ICLK
t
T
2
CDELAY
T
2
CDELAY
ICLK
---------------------------------
1
+
=
Summary of Contents for TMS470R1x
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