MibSPI Operation Modes
8
SPIDAT0 register. When the selected number of bits has been transmitted,
the data is transferred to the SPIBUF register for the CPU to read. Data is
stored right-justified in SPIBUF.
When the specified number of bits has been shifted through the SPIDAT0
register, the following events occur:
❏
The RXINTFLAG bit (SPICTRL3.0) is set to 1
❏
The SPIDAT0 register contents transfer to the SPIBUF register
❏
An interrupt is asserted if the RXINTEN bit (SPICTRL3.1) is set to 1
In slave mode configuration (MASTER = 0 and CLKMOD = 0), data shifts out
on the SPISOMI pin and in on the SPISIMO pin. The SPICLK pin is used as
the input for the serial shift clock, which is supplied from the external network
master. The transfer rate is defined by this clock.
Data written to the SPIDAT0 register is transmitted to the network when the
SPICLK signal is received from the network master. To receive data, the
MibSPI waits for the network master to send the SPICLK signal and then
shifts data on the SPISIMO pin into the SPIDAT0 register. If data is to be
transmitted by the slave simultaneously, it must be written to the SPIDAT0
register before the beginning of the SPICLK signal.
When the MIPSPI mode is enabled, the three-pin option works by setting all
the SPISCS pins in GPIO mode. The chip-select field in the buffers becomes
meaningless.
2.3
MibSPI Operation; Four-Pin Option
The three-pin option and the four-pin options of the MibSPI are identical in the
master mode (CLKMOD = 1), except that the four-pin option uses either
SPIENA or SPISCS [7:0] pins. The I/O direction of these pins is determined
by the CLKMOD control bit as MibSPI not general purpose I/O.
2.3.1
Four-Pin Option with SPISCS [7:0]
Compatibility mode
To use the SPISCS [0] as an automatic chip select pin, the SPISCS [0] pin
must be configured to be functional (SPIPC6.4 = 1). In this mode, the master
will drive this signal low when data has been written to SPIDAT1 and then
drive the pin high again after a character transmission has completed. If data
is written to SPIDAT0, SPISCS [0] remains high (see Figure 3).
Summary of Contents for TMS470R1x
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