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EMIF System Control Register (ESCR) [1C33h]

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1-49.

EMIF Clock Divider Register (ECDR) [1C26h]

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SPRUFX5A – October 2010 – Revised November 2010

List of Figures

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Summary of Contents for TMS3320C5515

Page 1: ...TMS3320C5515 DSP System User s Guide Literature Number SPRUFX5A October 2010 Revised November 2010...

Page 3: ...k Management 34 1 5 4 Static Power Management 46 1 5 5 Power Configurations 50 1 6 Interrupts 53 1 6 1 IFR and IER Registers 54 1 6 2 Interrupt Timing 55 1 6 3 Timer Interrupt Aggregation Flag Registe...

Page 4: ...4 0x1C2C 49 1 24 RAM Sleep Mode Control Register5 0x1C2D 49 1 25 IFR0 and IER0 Bit Locations 54 1 26 IFR1 and IER1 Bit Locations 55 1 27 Die ID Register 0 DIEIDR0 1C40h 58 1 28 Die ID Register 1 DIEID...

Page 5: ...ystem Control Register ESCR 1C33h 76 1 49 EMIF Clock Divider Register ECDR 1C26h 77 5 SPRUFX5A October 2010 Revised November 2010 List of Figures Submit Documentation Feedback Copyright 2010 Texas Ins...

Page 6: ...gister 1 PCGCR1 Field Descriptions 39 1 25 Peripheral Clock Gating Configuration Register 2 PCGCR2 Field Descriptions 41 1 26 Peripheral Clock Stop Request Acknowledge Register CLKSTOP Field Descripti...

Page 7: ...ster DMAIER Field Descriptions 72 1 56 DMAn Channel Event Source Register 1 DMAnCESR1 Field Descriptions 73 1 57 DMAn Channel Event Source Register 2 DMAnCESR2 Field Descriptions 73 1 58 Peripheral So...

Page 9: ...r SPRUFO1A TMS320C5515 14 05 04 VC05 VC04 Digital Signal Processor DSP Inter Integrated Circuit I2C Peripheral User s Guide This document describes the inter integrated circuit I2C peripheral in the T...

Page 10: ...the TMS320C5515 14 05 04 Digital Signal Processor DSP devices The DMA controller is used to move data among internal memory external memory and peripherals without intervention from the CPU and in the...

Page 11: ...s document describes various aspects of the TMS320C5504 digital signal processor DSP including system memory device clocking options and operation of the DSP clock generator power management features...

Page 13: ...red by portable audio wireless audio devices industrial controls software defined radio fingerprint biometrics and medical applications The C5515 DSP consists of the following primary components A C55...

Page 14: ...and software driven auto scaling feature provides good precision vs cycle count trade off Single stage and double stage modes enabling computation of one or two stages in one pass thus handling odd po...

Page 15: ...r direct memory access DMA controllers each with four independent channels One external memory interface EMIF with 21 bit address and 16 bit data The EMIF has support for mobile SDRAM and non mobile S...

Page 16: ...f memory types The on chip dual access RAM allows two accesses to a given block during the same cycle The device has 8 blocks of 8K bytes of dual access RAM The on chip single access RAM allows one ac...

Page 17: ...USB controller does not have access to DARAM E The CS0 space can be accessed by CS0 only or by CS0 and CS1 1 2 1 1 On Chip Dual Access RAM DARAM The DARAM is located in the CPU byte address range 00...

Page 18: ...00h 0009 FFFFh SARAM 8 02 0000h 02 1FFFh 000A 0000h 000A 1FFFh SARAM 9 02 2000h 02 3FFFh 000A 2000h 000A 3FFFh SARAM 10 02 4000h 02 5FFFh 000A 4000h 000A 5FFFh SARAM 11 02 6000h 02 7FFFh 000A 6000h 00...

Page 19: ...elect space The external memory interface EMIF provides the means for the DSP to access external memories and other devices including NOR Flash NAND Flash SRAM mSDRAM and SDRAM see section 1 5 for lim...

Page 20: ...red the CPU must wait until the very last EMIF register update takes effect before trying to access the external memory The users should consult the respective peripheral user s guide to determine if...

Page 21: ...illator connect the RTC_XI pin to CVDDRTC and the RTC_XO pin to ground The USB oscillator is powered down at hardware reset It must be enabled by the NNN register and must be allowed to settle for an...

Page 22: ...I2S3CG I2S3 PCGCR2 SARCG SAR PCGCR2 LCDCG LCD Controller PCGCR1 MMCSD0CG MMC SD0 PCGCR1 MMCSD1CG MMC SD1 USBPHYCLK RTC Clock LS RTC OSC RTC_XI RTC_XO 32 768 KHz RTC_CLKOUT RTC LS CLKREF 1 1 1 1 2 Acc...

Page 23: ...er 1 is the master clock gater Asserting this bit causes the main system clock SYSCLK to stop and therefore the CPU and all peripherals no longer receive clocks The WAKEUP pin INT0 INT1 pin or RTC int...

Page 24: ...ble 1 10 for allowed values of PLLIN PLLOUT and SYSCLK Keep in mind that programming the output divider with an odd divisor value other than 1 will result in a non 50 duty cycle SYSCLK This is not a p...

Page 25: ...ference Guide SWPU073 The slew rate i e dV dt of the CLKOUT pin can be controlled by the CLKOUTSR bits in the output slew rate control register OSRCR This feature allows for additional power savings w...

Page 26: ...ut approximately 36 MHz 1 4 3 Configuration 1 4 3 1 BYPASS MODE When the system clock generator is in the BYPASS MODE the clock generator is not used and the system clock SYSCLK is driven by either th...

Page 27: ...the input clock signal 1 4 3 2 1 Entering and Exiting the PLL MODE To enter the PLL_MODE from BYPASS_MODE first program the PLL to the desired frequency You must always ensure the PLL has completed i...

Page 28: ...mmed in the clock generator control registers The output frequency depends on primarily on three factors the reference divider value the PLL multiplier value and the output divider value see Figure 1...

Page 29: ...ing to PLL_MODE 1 Make sure the clock generator is in BYPASS MODE by setting SYSCLKSEL 0 2 Set CLR_CNTL 0 in CGCR1 3 Program RDRATIO M and RDBYPASS in CGCR2 according to your required settings 4 Progr...

Page 30: ...Generator Control Register 2 CGCR2 1C21h The clock generator control register 2 CGCR2 is shown in Figure 1 7 and described in Table 1 14 Figure 1 7 Clock Generator Control Register 2 CGCR2 1C21h 15 1...

Page 31: ...1C23h The clock generator control register 4 CGCR4 is shown in Figure 1 9 and described in Table 1 16 Figure 1 9 Clock Generator Control Register 4 CGCR4 1C23h 15 10 9 8 7 0 Reserved OUTDIVEN Reserve...

Page 32: ...his status register exists to indicate that switching from the PLL BYPASS_MODE to the PLL_MODE was successful or not Logic exists on the chip to prevent switching to PLL_MODE if the PLL has its PWRDN...

Page 33: ...ternal memory of the DSP can also be placed in a low leakage power mode while preserving the memory contents The operating voltage and drive strength of the I O pins can also be reduced to decrease I...

Page 34: ...he 10 bit SAR VDDA_ANA Nominal supply voltage is 1 3 V This domain can be powered from the on chip analog LDO output pin ANA_LDOO Note When externally powered this domain must be always powered for pr...

Page 35: ...all peripherals and CPU ports are disabled To get the minimum power consumption make sure to disable all peripherals and CPU ports first and then enable only necessary peripherals and CPU ports before...

Page 36: ...T remains active after execution of an IDLE instruction 1 IPORT is disabled after execution of an IDLE instruction 7 MPORTI Memory port idle control bit The memory port is used for all DMA LCD DMA and...

Page 37: ...dle status bit 0 CPU is active 1 CPU is disabled 1 5 3 1 2 Valid Idle Configurations Not all of the values that you can write to the idle configuration register ICR provide valid idle configurations T...

Page 38: ...nal reaches the DSP core these domains are un idled automatically Once the CPU is enabled it takes 3 CPU cycles to detect the interrupt in the IFR Note that HWA and MPORT have to be manually enabled a...

Page 39: ...2S2 clock gate control bit This bit is used to enable and disable the I2S2 peripheral clock 0 Peripheral clock is active 1 Peripheral clock is disabled 13 TMR2CG Timer 2 clock gate control bit This bi...

Page 40: ...the DMA controller 0 0 Peripheral clock is active 1 Peripheral clock is disabled 2 UARTCG UART clock gate control bit This bit is used to enable and disable the UART peripheral clock NOTE You must req...

Page 41: ...DMA2CG DMA controller 2 clock gate control bit This bit is used to enable and disable the DMA controller 2 peripheral clock 0 Peripheral clock is active 1 Peripheral clock is disabled 3 DMA1CG DMA con...

Page 42: ...for its clock to be stopped The UART clock should not be stopped until this bit is set to 1 0 The request to stop the peripheral clock has not been acknowledged 1 The request to stop the peripheral c...

Page 43: ...write to these registers the idle instruction is not required 1 5 3 3 Clock Generator Domain Clock Gating To save power the system clock generator can be placed in its BYPASS MODE and its PLL can be...

Page 44: ...he USB peripheral clock by setting USBCG 0 in the peripheral clock gating control register 2 PCGCR2 4 Clear the USB clock stop request bit USBCLKSTREQ in the CLKSTOP register 5 Clear the SUSPENDM bit...

Page 45: ...t can also be used when an external oscillator bias resistor is connected between the USB_MXI and USB_MXO pins but this is not a recommended configuration 2 USBOSCDIS USB oscillator disable bit 0 USB...

Page 46: ...not be used since the POR gets powered down and the POWERGOOD signal would not get generated properly After this bit is asserted the on chip LDOs Analog POR and the Bandgap reference can only be re en...

Page 47: ...WAKEUP pin assertion has occurred 0 External event interrupt has not occurred 1 External event interrupt occurred write 1 to clear 4 DAYFL Day event has occurred 0 Periodic Day event has not occurred...

Page 48: ...lost NOTE You must wait at least 10 CPU clock cycles after taking memory out of a low power mode before initiating any read or write access Table 1 30 summarizes the power modes for both DARAM and SA...

Page 49: ...te R Read only n value after reset Figure 1 23 RAM Sleep Mode Control Register4 0x1C2C 15 14 13 12 11 10 9 8 SARAM23 SARAM23 SARAM22 SARAM22 SARAM21 SARAM21 SARAM20 SARAM20 SLPZVDD SLPZVSS SLPZVDD SLP...

Page 50: ...s and CPU ports before using them to be sure these are not idle Table 1 31 Power Configurations Steps to Enter Clock Available Methods for Power Power Domain and Power Changing Exiting Clock and Confi...

Page 51: ...nput by setting WU_DIR 1 in the RTC power management register RTCPMGT If using the RTC alarm or periodic interrupt as a wake up event the RTCINTEN bit must be set in the RTC interrupt enable register...

Page 52: ...e CPU domain system to enable or disable the specified clocks The IDLE instruction cannot be executed in parallel with another instruction To exit the IDLE3 power configuration follow these steps 1 Ge...

Page 53: ...nsmit interrupt 0 I2S0 transmit or MMC SD0 interrupt UART SINT6 0x30 9 UART interrupt PROG1 SINT7 0x38 10 Programmable receive interrupt 1 I2S0 receive or MMC SD0 SDIO interrupt DMA SINT8 0x40 11 DMA...

Page 54: ...hould always be written with 0 9 PROG2 1 0 Programmable transmit interrupt 2 flag mask bit This bit is used as either the I2S1 transmit interrupt flag mask bit or the MMC SD1 interrupt flag mask bit T...

Page 55: ...errupt flag mask bit 1 RCV3 1 0 I2S3 receive interrupt flag mask bit 0 XMT3 1 0 I2S3 transmit interrupt flag mask bit 1 6 2 Interrupt Timing The interrupt signals on the external interrupts pins INT0...

Page 56: ...t aggregation flag registers IOINTFLG1 and IOINTFLG2 are secondary flag registers that serve this purpose If any of the GPIO pins are configured as inputs they can be enabled to accept external signal...

Page 57: ...gisters that are intended for use in TI chip manufacturing but can be used by users as a 128 bit unique ID for each device These registers are summarized in the following table Table 1 35 Die ID Regis...

Page 58: ...e ID Register 1 DIEIDR1 1C41h 15 14 13 0 Reserved DIEID1 R R LEGEND R Read only n value after reset Table 1 37 Die ID Register 1 DIEIDR1 Field Descriptions Bit Field Value Description 15 14 Reserved 0...

Page 59: ...1 31 and described in Table 1 40 Figure 1 31 Die ID Register 4 DIEIDR4 1C44h 15 6 5 0 Reserved DIEID4 R R LEGEND R Read only n value after reset Table 1 40 Die ID Register 4 DIEIDR4 Field Description...

Page 60: ...0 Reserved 1 7 2 8 Die ID Register 7 DIEIDR7 1C47h The die ID register 7 DIEIDR7 is shown in Figure 1 34 and described in Table 1 43 Figure 1 34 Die ID Register 7 DIEIDR7 1C47h 15 14 1 0 Reserved CHE...

Page 61: ...A xx pin retains its EMIF functionality Before modifying the values of the external bus selection register you must clock gate all affected peripherals through the Peripheral Clock Gating Control Regi...

Page 62: ...Control Bits The bits control the pin multiplexing of the MMC1 I2S1 and GPIO pins on serial port 1 00 Mode 0 MMC SD1 All 6 signals of the MMC SD1 module are routed to the 6 external signals of the se...

Page 63: ...Control All three LDOs can be simultaneously disabled via software by writing to either the BG_PD bit or the LDO_PD bit in the RTCPMGT register see Figure 1 36 When the LDOs are disabled via this mech...

Page 64: ...bit is asserted the on chip LDOs Analog POR and the Bandgap reference can be re enabled by the WAKEUP pin high or the RTC alarm interrupt The Bandgap circuit will take about 100 msec to charge the ext...

Page 65: ...O is regulated to 1 05 V 0 USB_LDO_EN USB_LDO enable bit 0 USB_LDO output is disabled USB_LDOO pin is placed in high impedance Hi Z state 1 USB_LDO output is enabled USB_LDOO is regulated to 1 3 V Tab...

Page 66: ...mately the same The slower slew rate control can be used for power savings and has the greatest effect at lower DVDDIO and DVDDEMIF voltages The output slew rate control register OSRCR is shown in Fig...

Page 67: ...ing this bit to 1 disables the pin s internal pull down 0 Pin pull down is enabled 1 Pin pull down is disabled 11 S13PD Serial port 1 pin 3 pull down inhibit bit Setting this bit to 1 disables the pin...

Page 68: ...Register 2 PDINHIBR2 Field Descriptions Bit Field Value Description 15 Reserved 0 Reserved 14 INT1PU Interrupt 1 pin pull up inhibit bit Setting this bit to 1 disables the pin s internal pull up 0 Pin...

Page 69: ...e 1 41 Pull Down Inhibit Register 3 PDINHIBR3 1C19h 15 14 13 12 11 10 9 8 PD15PD PD14PD PD13PD PD12PD PD11PD PD10PD PD9PD PD8PD R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 7 6 5 4 3 2 1 0 PD7PD PD...

Page 70: ...D Parallel port pin 3 pull down inhibit bit Setting this bit to 1 disables the pin s internal pull down 0 Pin pull down is enabled 1 Pin pull down is disabled 2 PD2PD Parallel port pin 2 pull down inh...

Page 71: ...ved Reserved Reserved Reserved 1010v Reserved Reserved Reserved Reserved 1011b Reserved Reserved Reserved Reserved 1100b Timer 0 event Timer 0 event Timer 0 event Timer 0 event 1101b Timer 1 event Tim...

Page 72: ...H2IF DMA2CH1IF DMA2CH0IF RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 DMA1CH3IF DMA1CH2IF DMA1CH1IF DMA1CH0IF DMA0CH3IF DMA0CH2IF DMA0CH1IF DMA0CH0IF RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0...

Page 73: ...Channel 1 synchronization events When SYNCMODE 1 in a channel s DMACHmTCR2 the CH1EVT bits in the DMAnCESR registers specify the synchronization event for activity in the DMA controller See Table 1 5...

Page 74: ...ister initiates the reset sequence for the associated peripherals The associated peripherals will be held in reset for the duration of clock cycles set in the PSRCR register and they should not be acc...

Page 75: ...should not be accessed 1 PG1_RST Peripheral group 1 software reset bit Drives the EMIF and all three timer reset signal Write 0 Writing zero has no effect Write 1 Writing one starts resetting the peri...

Page 76: ...emory for every CPU word access The USB system control register USBSCR is described in Section 1 5 3 4 2 Table 1 61 Effect of USBSCR BYTEMODE Bits on USB Access BYTEMODE Setting CPU Access to USB Regi...

Page 77: ...IF clock divider register ECDR is shown in Figure 1 49 and described in Table 1 63 Figure 1 49 EMIF Clock Divider Register ECDR 1C26h 15 1 0 Reserved EDIV R 0 R W 1 LEGEND R W Read Write R Read only n...

Page 78: ...h statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury...

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