Texas Instruments TMS320VC5509, Reference Manual

Page: 33 / 285

Clocking and Framing Data
McBSP Operation 2-10 SPRU592E
Equation 2 − 2. Maximum Frame Frequency of a McBSP
Maximum Frame Frequency
+
Clock Frequency
Number of Bits Per Frame
Figure 2 − 6 shows the McBSP operating at maximum packet frequency. At
maximum packet frequency, the data bits in consecutive packets are
transmitted contiguously with no inactivity between bits.
Figure 2 − 6. McBSP Operating at Maximum Packet Frequency
D(R/X)
FS(R/X)
CLK(R/X)
C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A2
If there is a 1-bit data delay as shown in this figure, the frame-synchronization
pulse overlaps the last bit transmitted in the previous frame. Effectively, this
permits a continuous stream of data, making frame-synchronization pulses
redundant. Theoretically, only an initial frame-synchronization pulse is
required to initiate a multipacket transfer.
The McBSP supports operation of the serial port in this fashion by ignoring the
successive frame-sync pulses. Data is clocked in to the receiver, or clocked
out of the transmitter, during every clock cycle.
Note:
For XDATDLY = 0 (0-bit data delay), the first bit of data is transmitted
asynchronously to the internal transmit clock signal (CLKX).
Note:
On the TMS320VC5501 and TMS320VC5502 devices, if a 0-bit delay and
an external clock are used, the transfer shown in Figure 2 − 6 can only be
achieved if the frame-sync ignore bit is set to 1. If the frame-sync ignore bit
is 0, an additional clock cycle is required between frames.