Texas Instruments TMS320VC5509, Reference Manual

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Pin Control Register (PCR)
12-39 McBSP Registers SPRU592E
Figure 12 − 8. Pin Control Register (PCR)
15 14 13 12 11 10 9 8
Reserved IDLEEN
†
XIOEN RIOEN FSXM FSRM CLKXM CLKRM
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
SCLKME CLKSSTAT DXSTAT DRSTAT FSXP FSRP CLKXP CLKRP
R/W-0 R-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R = Read; W = Write; - n = Value after reset
†
On TMSVC5501 and TMSVC5502 devices, bit 14 is reserved and should be written as 0. On TMS320VC5503/5507/5509 and
TMS320VC5510 devices, bit 14 provides the IDLEEN function described in Table 12
− 11.
Table 12 − 11. PCR Bit Descriptions
Bit Field Value Description
15 Reserved 0 Reserved bit (not available for your use). It is a read-only bit and returns a
0 when read.
14 IDLEEN
or
Reserved On TMS320VC5503/5507/5509 and TMS320VC5510 devices: This bit is
the idle enable bit. If the PERIPH idle domain is configured to be idle and
IDLEEN = 1, the McBSP stops and enters a low-power state.
On the TMS320VC5501 and TMS320VC5502 devices: This bit is reserved
and should be written as 0. The IDLEEN function is implemented in the
Peripheral Idle Control Register (PICR). For more information on the PICR,
see the
TMS320VC5501 Fixed-Point Digital Signal Processor Data Manual
(literature number SPRS206) or the TMS320VC5502 Fixed-Point Digital
Signal Processor Data Manual (literature number SPRS166).
0 The McBSP remains active when the PERIPH domain is idled.
1 If the PERIPH domain is idle (PERIS = 1 in the idle status register), the
McBSP is stopped in a low-power state.
13 XIOEN Transmit I/O enable bit. When the transmitter is in reset (XRST = 0), XIOEN
can configure certain McBSP pins as general-purpose I/O (GPIO) pins. For
a summary, see the table that follows the RIOEN bit description.
0 The CLKX, FSX, DX, and CLKS pins are serial port pins.
1 If XRST = 0, the CLKX, FSX, and DX pins are GPIO pins. The CLKS is also
a GPIO pin if RRST = 0 and RIOEN = 1.