Texas Instruments TMS320VC5509, Reference Manual

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Setting the SRG Clock Mode (Choosing an Input Clock)
Receiver Configuration 7-40 SPRU592E
7.23 Setting the SRG Clock Mode (Choosing an Input Clock)
The bits shown in Figure 7 − 26 and described in Table 7 − 28 determine the
source for the SRG clock. Not all C55x devices have a CLKS pin; check the
device-specific data manual.
Figure 7 − 26. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
PCR
15 8 7 6 0
SCLKME
R/W-0
SRGR2
15 14 13 12 0
CLKSM
R/W-1
Legend: R = Read; W = Write; - n = Value after reset
Table 7 − 28. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
Register Bit Name Function
PCR
SRGR2 7
13 SCLKME
CLKSM Sample Rate Generator Clock Mode
SCLKME = 0
CLKSM = 0 Sample rate generator clock derived from CLKS pin
SCLKME = 0
CLKSM = 1 Sample rate generator clock derived from McBSP internal
input clock (This is the condition forced by a DSP reset.)
SCLKME = 1
CLKSM = 0 Sample rate generator clock derived from CLKR pin
SCLKME = 1
CLKSM = 1 Sample rate generator clock derived from CLKX pin
7.23.1 About the SRG Clock Mode
The sample rate generator can produce a clock signal (CLKG) for use by the
receiver, the transmitter, or both, but CLKG is derived from an input clock.
Table 7
− 28 shows the four possible sources of the input clock.