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Texas Instruments TMS320VC5402 Datasheet Download Page 29

        

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000

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McBSP control registers and subaddresses

The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location.
The serial port subbank address (SPSA) register is used as a pointer to select a particular register within the
subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected register.
Table 11 shows the McBSP control registers and their corresponding sub-addresses.

Table 11. McBSP Control Registers and Subaddresses

McBSP0

McBSP1

NAME

ADDRESS

NAME

ADDRESS

SUB-

ADDRESS

DESCRIPTION

ÁÁÁÁÁ

ÁÁÁÁÁ

SPCR10

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

SPCR11

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

00h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Serial port control register 1

ÁÁÁÁÁ

SPCR20

ÁÁÁÁ

39h

ÁÁÁÁÁ

SPCR21

ÁÁÁÁ

49h

ÁÁÁÁÁ

01h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Serial port control register 2

ÁÁÁÁÁ

ÁÁÁÁÁ

RCR10

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

RCR11

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

02h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receive control register 1

ÁÁÁÁÁ

ÁÁÁÁÁ

RCR20

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

RCR21

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

03h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receive control register 2

ÁÁÁÁÁ

ÁÁÁÁÁ

XCR10

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

XCR11

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

04h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmit control register 1

ÁÁÁÁÁ

ÁÁÁÁÁ

XCR20

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

XCR21

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

05h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmit control register 2

ÁÁÁÁÁ

ÁÁÁÁÁ

SRGR10

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

SRGR11

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

06h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Sample rate generator register 1

ÁÁÁÁÁ

ÁÁÁÁÁ

SRGR20

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

SRGR21

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

07h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Sample rate generator register 2

ÁÁÁÁÁ

ÁÁÁÁÁ

MCR10

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

MCR11

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

08h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Multichannel register 1

ÁÁÁÁÁ

ÁÁÁÁÁ

MCR20

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

MCR21

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

09h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Multichannel register 2

ÁÁÁÁÁ

RCERA0

ÁÁÁÁ

39h

ÁÁÁÁÁ

RCERA1

ÁÁÁÁ

49h

ÁÁÁÁÁ

0Ah

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receive channel enable register partition A

ÁÁÁÁÁ

ÁÁÁÁÁ

RCERB0

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

RCERB1

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

0Bh

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receive channel enable register partition B

ÁÁÁÁÁ

ÁÁÁÁÁ

XCERA0

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

XCERA1

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

0Ch

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmit channel enable register partition A

ÁÁÁÁÁ

ÁÁÁÁÁ

XCERB0

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

XCERB1

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

0Dh

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmit channel enable register partition B

ÁÁÁÁÁ

ÁÁÁÁÁ

PCR0

ÁÁÁÁ

ÁÁÁÁ

39h

ÁÁÁÁÁ

ÁÁÁÁÁ

PCR1

ÁÁÁÁ

ÁÁÁÁ

49h

ÁÁÁÁÁ

ÁÁÁÁÁ

0Eh

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Pin control register

DMA subbank addressed registers

The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register
within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register with
autoincrement (DMSDI) is used to access (read or write) the selected register.

When the DMSDI register is used to access the subbank, the subbank address is automatically
post-incremented so that a subsequent access affects the next register within the subbank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 12 shows the DMA controller
subbank addressed registers and their corresponding subaddresses.

Summary of Contents for TMS320VC5402

Page 1: ...allel Store and Parallel Load Conditional Store Instructions Fast Return From Interrupt On Chip Peripherals Software Programmable Wait State Generator and Programmable Bank Switching On Chip Phase Locked Loop PLL Clock Generator With Internal Oscillator or External Clock Source Two Multichannel Buffered Serial Ports McBSPs Enhanced 8 Bit Parallel Host Port Interface HPI8 Two 16 Bit Timers Six Chan...

Page 2: ...tor With External Crystal 36 Divide By Two Clock Option PLL Disabled 37 Multiply By N Clock Option 38 Memory and Parallel I O Interface Timing 39 Ready Timing For Externally Generated Wait States 45 HOLD and HOLDA Timings 49 Reset BIO Interrupt and MP MC Timings 50 Instruction Acquisition IAQ Interrupt Acknowledge IACK External Flag XF and TOUT Timings 52 Multichannel Buffered Serial Port Timing 5...

Page 3: ... operational flexibility and speed of this DSP is a highly specialized instruction set Separate program and data spaces allow simultaneous access to program instructions and data providing the high degree of parallelism Two read operations and one write operation can be performed in a single cycle Instructions with parallel store and application specific instructions can fully utilize this archite...

Page 4: ... 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC NC HCNTL0 SS BCLKR0 BCLKR1 BFSR0 BFSR1 BDR0 HCNTL1 BDR1 BCLKX0 BCLKX1 SS DD SS HD0 BDX0 BDX1 IACK HBIL NM...

Page 5: ...tion continued TMS320VC5402 GGU PACKAGE BOTTOM VIEW A B D C E F H J L M K N G 1 2 3 4 5 6 7 8 10 12 11 13 9 The pin assignments table to follow lists each signal quadrant and BGA ball number for the TMS320VC5402GGU 144 pin BGA package which is footprint compatible with the LC548 and LC VC549 devices ...

Page 6: ...D8 VSS F3 TDI H11 VSS L6 D14 C8 NC F2 TRST H12 HINT TOUT1 M6 D15 B8 CVDD F1 TCK H13 CVDD N6 HD5 A8 HCS G2 TMS G12 BFSX0 M7 CVDD B7 HR W G1 NC G13 BFSX1 N7 NC A7 READY G3 CVDD G11 HRDY L7 HDS1 C7 PS G4 HPIENA G10 DVDD K7 VSS D7 DS H1 VSS F13 VSS N8 HDS2 A6 IS H2 CLKOUT F12 HD0 M8 DVDD B6 R W H3 HD3 F11 BDX0 L8 A0 C6 MSTRB H4 X1 F10 BDX1 K8 A1 D6 IOSTRB J1 X2 CLKIN E13 IACK N9 A2 A5 MSC J2 RS E12 HB...

Page 7: ...pins These bus holders also eliminate the need for external bias resistors on unused pins When the data bus is not being driven by the 5402 the bus holders keep the pins at the previous logic level The data bus holders on the 5402 are disabled at reset and can be enabled disabled via the BH bit of the bank switching control register BSCR INITIALIZATION INTERRUPT AND RESET OPERATIONS IACK O Z Inter...

Page 8: ... READY I Data ready READY indicates that an external device is prepared for a bus transaction to be completed If the device is not ready READY is low the processor waits one cycle and checks READY again Note that the processor performs ready detection if at least two software wait states are programmed The READY signal is not sampled until the completion of the software wait states R W O Z Read wr...

Page 9: ...eceive input BFSR0 BFSR1 I O Z Frame synchronization pulse for receive input BFSR can be configured as an input or an output it is configured as an input following reset The BFSR pulse initiates the receive data process over BDR BCLKX0 BCLKX1 I O Z Transmit clock BCLKX serves as the serial shift clock for the McBSP transmitter BCLKX can be configured as an input or an output it is configured as an...

Page 10: ...bled Once the HPI is disabled the HPIENA pin has no effect until the 5402 is reset SUPPLY PNS CVDD S VDD Dedicated 1 8 V power supply for the core CPU DVDD S VDD Dedicated 3 3 V power supply for the I O pins VSS S Ground TEST PINS TCK I IEEE standard 1149 1 test clock TCK is normally a free running clock signal with a 50 duty cycle The changes on the test access port TAP of input signals TMS and T...

Page 11: ... output by way of the IEEE standard 1149 1 scan system When TRST is driven low EMU1 OFF is configured as OFF The EMU1 OFF signal when active low puts all output drivers into the high impedance state Note that OFF is used exclusively for testing and emulation purposes not for multiprocessing applications The OFF feature is selected by the following pin combinations TRST low EMU0 high EMU1 OFF low I...

Page 12: ...nstruction to the start of the bootloader program The standard 5402 bootloader provides different ways to download the code to accomodate various system requirements Parallel from 8 bit or 16 bit wide EPROM Parallel from I O space 8 bit or 16 bit mode Serial boot from serial ports 8 bit or 16 bit mode Host port interface boot The standard on chip ROM layout is shown in Table 1 Table 1 Standard On ...

Page 13: ...rogram space These vectors are soft meaning that the processor when taking the trap loads the program counter PC with the trap address and executes the code at the vector location Four words are reserved at each vector location to accommodate a delayed branch instruction either two 1 word instructions or one 2 word instruction which allows branching to the appropriate interrupt service routine wit...

Page 14: ... 001Eh At a hardware reset the XPC is initialized to 0 Six extra instructions for addressing extended program space These six instructions affect the XPC FB D pmad 20 bits Far branch FBACC D Accu 19 0 Far branch to the location specified by the value in accumulator A or accumulator B FCALL D pmad 20 bits Far call FCALA D Accu 19 0 Far call to the location specified by the value in accumulator A or...

Page 15: ...er 16K External 0 FFFF Page 0 64K Words 1 4000 1 FFFF Page 1 Upper 48K External 2 4000 2 FFFF Page 2 Upper 48K External F 4000 F FFFF Page 15 Upper 48K External See Figure 1 The lower 16K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0 If the OVLY bit is set to 1 the on chip RAM is mapped to the lower 16K words of all program space pages Figure 3 Extended Program M...

Page 16: ...automatically disabled Disabling the wait state generator clocks reduces the power comsumption of the 5402 The software wait state register SWWSR controls the operation of the wait state generator The 14 LSBs of the SWWSR specify the number of wait states 0 to 7 to be inserted for external memory accesses to five separate address ranges This allows a different number of wait states for each of the...

Page 17: ...he field value 0 7 corresponds to the base number of wait states for external program space accesses within the following addresses XPA 0 x8000 xFFFFh XPA 1 The upper program space bit field has no effect on wait states The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states 2 0 Program 1 Program space The field value 0 7 corresponds to the base number...

Page 18: ...ank sizes of 4K words to 64K words are allowed 11 PS DS 1 Program read data read access Inserts an extra cycle between consecutive accesses of program read and data read or data read and program read PS DS 0 No extra cycles are inserted by this feature PS DS 1 One extra cycle is inserted between consecutive data and program reads 10 3 Reserved 0 These bits are reserved and are unaffected by writes...

Page 19: ...HPI8 functions as a slave and enables the host processor to access the on chip memory of the 5402 A major enhancement to the 5402 HPI over previous versions is that it allows host access to the entire on chip memory range of the DSP The HPI8 memory map is identical to that of the DMA controller shown in Figure 7 The host and the DSP both have access to the on chip RAM at all times and host accesse...

Page 20: ...ction of data sizes including 8 12 16 20 24 or 32 bits µ law and A law companding Programmable polarity for both frame synchronization and data clocks Programmable internal clock and frame generation The McBSPs consist of separate transmit and receive channels that operate independently The external interface of each McBSP consists of the following pins BCLKX Transmit reference clock BDX Transmit ...

Page 21: ...ch frame represents a time division multiplexed TDM data stream In using TDM data streams the CPU may only need to process a few of them Thus to save memory and bus bandwidth multichannel selection allows independent enabling of particular channels for transmission and reception Up to 32 channels in a stream of up to 128 channels can be enabled The clock stop mode CLKSTP in the McBSP provides comp...

Page 22: ...hould be noted that the X2 CLKIN pin is referenced to the device 1 8V power supply CVdd rather than the 3V I O supply DVdd Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2 CLKIN pin The software programmable PLL features a high level of flexibility and includes a clock scaler that provides various clock multiplier ratios capability t...

Page 23: ...than the CPU for internal accesses Each channel has independently programmable priorities Each channel s source and destination address registers can have configurable indexes through memory on each read and write transfer respectively The address may remain constant be post incremented post decremented or be adjusted by a programmable value Each read or write transfer may be initialized by select...

Page 24: ...me to be transferred Frame count This 8 bit value defines the total number of frames in the block transfer The maximum number of frames per block transfer is 128 FRAME COUNT 0ffh The counter is decremented upon the last read transfer in a frame transfer Once the last frame is transferred the selected 8 bit counter is reloaded with the DMA global frame reload register DMGFR if the AUTOINIT bit is s...

Page 25: ...he available modes are shown in Table 6 Table 6 DMA Interrupts MODE DINM IMOD INTERRUPT ABU non decrement 1 0 At full buffer only ABU non decrement 1 1 At half buffer and full buffer Multi Frame 1 0 At block transfer complete DMCTRn DMSEFCn 7 0 0 Multi Frame 1 1 At end of frame and end of block DMCTRn 0 Either 0 X No interrupt generated Either 0 X No interrupt generated DMA controller synchronizat...

Page 26: ...IFR bits 10 and 11 and DMA channel 1 shares an interrupt line with timer 1 IMR IFR bit 7 The interrupt source for DMA channel 0 is shared with a reserved interrupt source When the 5402 is reset the interrupts from these four DMA channels are deselected The INTSEL bit field in the DMA channel priority and enable control DMPREC register can be used to select these interrupts as shown in Table 8 Tabl...

Page 27: ...Status register 0 ST1 7 7 Status register 1 AL 8 8 Accumulator A low word 15 0 AH 9 9 Accumulator A high word 31 16 AG 10 A Accumulator A guard bits 39 32 BL 11 B Accumulator B low word 15 0 BH 12 C Accumulator B high word 31 16 BG 13 D Accumulator B guard bits 39 32 TREG 14 E Temporary register TRN 15 F Transition register AR0 16 10 Auxiliary register 0 AR1 17 11 Auxiliary register 1 AR2 18 12 Au...

Page 28: ...ÁÁÁÁÁÁ ÁÁÁÁÁÁ 39h ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ McBSP0 subbank data register ÁÁÁÁÁÁ ÁÁÁÁÁÁ McBSP 0 3Ah 3Bh Reserved ÁÁÁÁÁÁ ÁÁÁÁÁÁ GPIOCR ÁÁÁÁÁÁ ÁÁÁÁÁÁ 3Ch ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ General purpose I O pins control register ÁÁÁÁÁÁ ÁÁÁÁÁÁ GPIO ÁÁÁÁÁÁ ÁÁÁÁÁÁ GPIOSR ÁÁÁÁÁÁ ÁÁÁÁÁÁ 3Dh ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ General purpose I O pins status register ÁÁÁÁÁÁ ÁÁÁÁÁÁ ...

Page 29: ...ÁÁÁÁ 39h ÁÁÁÁÁ ÁÁÁÁÁ MCR11 ÁÁÁÁ ÁÁÁÁ 49h ÁÁÁÁÁ ÁÁÁÁÁ 08h ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Multichannel register 1 ÁÁÁÁÁ ÁÁÁÁÁ MCR20 ÁÁÁÁ ÁÁÁÁ 39h ÁÁÁÁÁ ÁÁÁÁÁ MCR21 ÁÁÁÁ ÁÁÁÁ 49h ÁÁÁÁÁ ÁÁÁÁÁ 09h ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Multichannel register 2 ÁÁÁÁÁ RCERA0 ÁÁÁÁ 39h ÁÁÁÁÁ RCERA1 ÁÁÁÁ 49h ÁÁÁÁÁ 0Ah ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receive channel enable register partition A ÁÁÁÁÁ ÁÁÁÁÁ RCERB0 ÁÁÁÁ ÁÁÁÁ 39h ÁÁÁÁ...

Page 30: ...ÁÁÁ ÁÁÁÁ 56h 57h ÁÁÁÁÁ ÁÁÁÁÁ 13h ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DMA channel 3 transfer mode control register ÁÁÁÁÁ ÁÁÁÁÁ DMSRC4 ÁÁÁÁ ÁÁÁÁ 56h 57h ÁÁÁÁÁ ÁÁÁÁÁ 14h ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DMA channel 4 source address register ÁÁÁÁÁ ÁÁÁÁÁ DMDST4 ÁÁÁÁ ÁÁÁÁ 56h 57h ÁÁÁÁÁ ÁÁÁÁÁ 15h ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DMA channel 4 destination address ...

Page 31: ...rupt 29 SINT30 60 3C Software interrupt 30 INT0 SINT0 64 40 3 External user interrupt 0 INT1 SINT1 68 44 4 External user interrupt 1 INT2 SINT2 72 48 5 External user interrupt 2 TINT0 SINT3 76 4C 6 Timer0 interrupt BRINT0 SINT4 80 50 7 McBSP 0 receive interrupt BXINT0 SINT5 84 54 8 McBSP 0 transmit interrupt Reserved DMAC0 SINT6 88 58 9 Reserved default or DMA channel 0 inter rupt The selection is...

Page 32: ...A channel 3 interrupt flag mask bit The selection is made in the DMPREC register 10 BRINT1 DMAC2 This bit can be configured as either the McBSP1 receive interrupt flag mask bit or the DMA channel 2 interrupt flag mask bit The selection is made in the DMPREC register 9 HPINT Host to 54x interrupt flag mask 8 INT3 External interrupt 3 flag mask 7 TINT1 DMAC1 This bit can be configured as either the ...

Page 33: ...c Instruction Set literature number SPRU179 Volume 4 Applications Guide literature number SPRU173 Volume 5 Enhanced Peripherals literature number SPRU302 The reference set describes in detail the TMS320C54x DSP generation of TMS320 DSP products currently available and the hardware and software applications including algorithms for fixed point TMS320 DSP devices For general background information o...

Page 34: ...3 V X2 CLKIN 1 35 CVDD 0 3 V DVDD 3 3 0 3 V TCK TRST 2 5 DVDD 0 3 All other inputs 2 DVDD 0 3 VIL Low level input voltage DVDD 3 3 0 3 V RS INTn NMI X2 CLKIN BIO BCLKR0 BCLKR1 BCLKX0 BCLKX1 HCS HDS1 HDS2 TCK CLKMDn 0 3 0 6 V DVDD 3 3 0 3 V All other inputs 0 3 0 8 IOH High level output current 300 µA IOL Low level output current 1 5 mA TC Operating case temperature 40 100 C Texas Instrument DSPs d...

Page 35: ...2 can be operated with an external clock source provided that the proper voltage levels be driven on the X2 CLKIN pin It should be noted that the X2 CLKIN pin is referenced to the device 1 8V power supply CVdd rather than the 3V I O supply DVdd Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2 CLKIN pin HPI input signals except for HP...

Page 36: ... operation and parallel resonant with an effective series resistance of 30 Ω and power dissipation of 1 mW The connection of the required circuit consisting of the crystal and two load capacitors is shown in Figure 10 The load capacitors C1 and C2 should be chosen such that the equation below is satisfied CL in the equation is the load specified for the crystal CL C1C2 C1 C2 recommended operating ...

Page 37: ...N pin timing requirements see Figure 11 MIN MAX UNIT tc CI Cycle time X2 CLKIN 20 ns tf CI Fall time X2 CLKIN 8 ns tr CI Rise time X2 CLKIN 8 ns This device utilizes a fully static design and therefore can operate with tc CI approaching The device is characterized at frequencies approaching 0 Hz switching characteristics over recommended operating conditions H 0 5tc CO see Figure 10 Figure 11 and ...

Page 38: ...le voltage levels of the X2 CLKIN pin timing requirements see Figure 12 MIN MAX UNIT Integer PLL multiplier N N 1 15 20 200 tc CI Cycle time X2 CLKIN PLL multiplier N x 5 20 100 ns tc CI Cycle time X2 CLKIN PLL multiplier N x 25 x 75 20 50 ns tf CI Fall time X2 CLKIN 8 ns tr CI Rise time X2 CLKIN 8 ns N Multiplication factor The multiplication factor and minimum X2 CLKIN cycle time should be chose...

Page 39: ... 0 ns Address PS and DS timings are all included in timings referenced as address switching characteristics over recommended operating conditions for a memory read MSTRB 0 see Figure 13 PARAMETER MIN MAX UNIT td CLKL A Delay time CLKOUT low to address valid 2 3 ns td CLKH A Delay time CLKOUT high transition to address valid 2 3 ns td CLKL MSL Delay time CLKOUT low to MSTRB low 1 3 ns td CLKL MSH D...

Page 40: ... memory and parallel I O interface timing continued PS DS R W MSTRB D 15 0 A 19 0 CLKOUT th D R th CLKL A R td CLKL MSH td CLKL A td CLKL MSL tsu D R ta A M ta MSTRBL th A D R th D MSTRBH NOTE A A 19 16 are always driven low during accesses to external data space Figure 13 Memory Read MSTRB 0 ...

Page 41: ...d CLKH RWL Delay time CLKOUT high to R W low 1 3 ns td CLKH RWH Delay time CLKOUT high to R W high 1 3 ns td RWL MSTRBL Delay time R W low to MSTRB low H 2 H 1 ns th A W Hold time address valid after CLKOUT high 1 3 ns th D MSH Hold time write data valid after MSTRB high H 3 H 6 ns tw SL MS Pulse duration MSTRB low 2H 2 ns tsu A W Setup time address valid before MSTRB low 2H 2 ns tsu D MSH Setup t...

Page 42: ...face timing continued PS DS R W MSTRB D 15 0 A 19 0 CLKOUT td CLKH RWH th A W td CLKL MSH tsu D MSH td CLKL D W tw SL MS tsu A W td CLKL MSL th D MSH td CLKL A td CLKH RWL td RWL MSTRBL td CLKH A ten D RWL tdis RWH D NOTE A A 19 16 are always driven low during accesses to external data space Figure 14 Memory Write MSTRB 0 ...

Page 43: ...s and IS timings are included in timings referenced as address switching characteristics over recommended operating conditions for a parallel I O port read IOSTRB 0 see Figure 15 PARAMETER MIN MAX UNIT td CLKL A Delay time CLKOUT low to address valid 2 3 ns td CLKH ISTRBL Delay time CLKOUT high to IOSTRB low 2 3 ns td CLKH ISTRBH Delay time CLKOUT high to IOSTRB high 2 3 ns th A IOR Hold time addr...

Page 44: ...h to IOSTRB high 2 3 ns td CLKL RWL Delay time CLKOUT low to R W low 1 3 ns td CLKL RWH Delay time CLKOUT low to R W high 1 3 ns th A IOW Hold time address valid after CLKOUT low 0 3 ns th D IOW Hold time write data after IOSTRB high H 3 H 7 ns tsu D IOSTRBH Setup time write data before IOSTRB high H 7 H 1 ns tsu A IOSTRBL Setup time address valid before IOSTRB low H 2 H 2 ns Address and IS timing...

Page 45: ...RB Hold time READY after IOSTRB low 5H ns tv MSCL Valid time MSC low after CLKOUT low 1 3 ns tv MSCH Valid time MSC high after CLKOUT low 1 3 ns The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles To generate wait states using READY at least two software wait states must be programmed These timings are included for reference only The crit...

Page 46: ...nerated wait states continued MSC MSTRB READY D 15 0 A 19 0 CLKOUT tv MSCH th RDY Wait State Generated by READY Wait States Generated Internally th RDY MSTRB tv RDY MSTRB tv MSCL tsu RDY NOTE A A 19 16 are always driven low during accesses to external data space Figure 18 Memory Write With Externally Generated Wait States ...

Page 47: ...rnally generated wait states continued tsu RDY MSC IOSTRB READY A 19 0 CLKOUT tv MSCH th RDY Wait State Generated by READY Wait States Generated Internally tv RDY IOSTRB tv MSCL th RDY IOSTRB NOTE A A 19 16 are always driven low during accesses to I O space Figure 19 I O Read With Externally Generated Wait States ...

Page 48: ...ly generated wait states continued IOSTRB MSC READY D 15 0 A 19 0 CLKOUT th RDY Wait State Generated by READY Wait States Generated Internally tv RDY IOSTRB tsu RDY tv MSCH tv MSCL th RDY IOSTRB NOTE A A 19 16 are always driven low during accesses to I O space Figure 20 I O Write With Externally Generated Wait States ...

Page 49: ... ns tdis CLKL RW Disable time R W high impedance from CLKOUT low 5 ns tdis CLKL S Disable time MSTRB IOSTRB high impedance from CLKOUT low 5 ns ten CLKL A Enable time address PS DS IS from CLKOUT low 2H 5 ns ten CLKL RW Enable time R W enabled from CLKOUT low 2H 5 ns ten CLKL S Enable time MSTRB IOSTRB enabled from CLKOUT low 2 2H 5 ns t Valid time HOLDA low after CLKOUT low 1 2 ns tv HOLDA Valid ...

Page 50: ...chronous 2H 2 ns tw INTL A Pulse duration INTn NMI low asynchronous 4H ns tw INTL WKP Pulse duration INTn NMI low for IDLE2 IDLE3 wakeup 10 ns tsu RS Setup time RS before X2 CLKIN low 5 ns tsu BIO Setup time BIO before CLKOUT low 7 10 ns tsu INT Setup time INTn NMI RS before CLKOUT low 7 10 ns tsu MPMC Setup time MP MC before CLKOUT low 5 ns The external interrupts INT0 INT3 NMI are synchronized t...

Page 51: ...BIO interrupt and MP MC timings continued BIO CLKOUT RS INTn NMI X2 CLKIN th BIO th RS tsu INT tw BIO S tsu BIO tw RSL tsu RS Figure 22 Reset and BIO Timings INTn NMI CLKOUT th INT tsu INT tsu INT tw INTL A tw INTH A Figure 23 Interrupt Timing MP MC RS CLKOUT tsu MPMC th MPMC Figure 24 MP MC Timing ...

Page 52: ...low to IAQ high 1 3 ns td A IAQ Delay time address valid to IAQ low 1 ns td CLKL IACKL Delay time CLKOUT low to IACK low 1 3 ns td CLKL IACKH Delay time CLKOUT low to IACK high 1 3 ns td A IACK Delay time address valid to IACK low 3 ns th A IAQ Hold time IAQ high after address invalid 2 ns th A IACK Hold time IACK high after address invalid 2 ns tw IAQL Pulse duration IAQ low 2H 2 ns tw IACKL Puls...

Page 53: ...ommended operating conditions for XF and TOUT H 0 5 tc CO see Figure 26 and Figure 27 PARAMETER MIN MAX UNIT t Delay time CLKOUT low to XF high 1 3 ns td XF Delay time CLKOUT low to XF low 1 3 ns td TOUTH Delay time CLKOUT low to TOUT high 0 4 ns td TOUTL Delay time CLKOUT low to TOUT low 0 4 ns tw TOUT Pulse duration TOUT 2H ns XF CLKOUT td XF Figure 26 XF Timing TOUT CLKOUT tw TOUT td TOUTL td T...

Page 54: ...rted switching characteristics for McBSP H 0 5tc CO see Figure 28 and Figure 29 PARAMETER MIN MAX UNIT tc BCKRX Cycle time BCLKR X BCLKR X int 4H ns tw BCKRXH Pulse duration BCLKR X high BCLKR X int D 2 D 2 ns tw BCKRXL Pulse duration BCLKR X low BCLKR X int C 2 C 2 ns t Delay time BCLKR high to internal BFSR valid BCLKR int 2 2 ns td BCKRH BFRV Delay time BCLKR high to internal BFSR valid BCLKR e...

Page 55: ...BFRV td BCKRH BFRV tr BCKRX tr BCKRX tw BCKRXL tc BCKRX tw BCKRXH RDATDLY 10b BDR RDATDLY 01b BDR RDATDLY 00b BDR BFSR ext BFSR int BCLKR Figure 28 McBSP Receive Timings td BCKXH BDXV td BCKXH BDXV tdis BCKXH BDXHZ td BCKXH BDXV td BDFXH BDXV XDATDLY 10b BDX XDATDLY 01b BDX XDATDLY 00b BDX n 2 Bit n 1 Bit 0 n 4 Bit n 1 n 3 n 2 Bit 0 n 3 n 2 Bit n 1 Bit 0 th BCKXL BFXH tf BCKRX tr BCKRX tw BCKRXL t...

Page 56: ... configured as a general purpose input switching characteristics for McBSP general purpose I O see Figure 30 PARAMETER MIN MAX UNIT td COH BGPIO Delay time CLKOUT high to BGPIOx output mode 0 5 ns BGPIOx refers to BCLKRx BFSRx BCLKXx BFSXx or BDXx when configured as a general purpose output tsu BGPIO COH th COH BGPIO td COH BGPIO CLKOUT BGPIOx Input Mode BGPIOx Output Mode BGPIOx refers to BCLKRx ...

Page 57: ...Z Disable time BDX high impedance following last data bit from BCLKX low C 2 C 3 ns tdis BFXH BDXHZ Disable time BDX high impedance following last data bit from BFSX high 2H 4 6H 17 ns td BFXL BDXV Delay time BFSX low to BDX valid 4H 2 8H 17 ns For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 T BCLKX period 1 CLKGDV 2H C BCLKX low pulse width T 2 when CL...

Page 58: ... BDXHZ Disable time BDX high impedance following last data bit from BCLKX low 2 4 6H 3 10H 17 ns td BFXL BDXV Delay time BFSX low to BDX valid D 2 D 4 4H 2 8H 17 ns For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 T BCLKX period 1 CLKGDV 2H C BCLKX low pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 2H when CLKGDV is even D BCLKX high pulse width...

Page 59: ... Disable time BDX high impedance following last data bit from BCLKX high D 2 D 3 ns tdis BFXH BDXHZ Disable time BDX high impedance following last data bit from BFSX high 2H 3 6H 17 ns td BFXL BDXV Delay time BFSX low to BDX valid 4H 2 8H 17 ns For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 T BCLKX period 1 CLKGDV 2H D BCLKX high pulse width T 2 when C...

Page 60: ...XHZ Disable time BDX high impedance following last data bit from BCLKX high 2 4 6H 3 10H 17 ns td BFXL BDXV Delay time BFSX low to BDX valid C 2 C 4 4H 2 8H 17 ns For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 T BCLKX period 1 CLKGDV 2H C BCLKX low pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 2H when CLKGDV is even D BCLKX high pulse width T...

Page 61: ...id after HRDY high 9 td DSH HYL Delay time DS high to HRDY low see Note 1 16 ns Case 1a Memory accesses when DMAC is active in 16 bit mode 18H 16 ns t Delay time DS high to HRDY high Case 1b Memory accesses when DMAC is active in 32 bit mode 26H 16 ns td DSH HYH Delay time DS high to HRDY high Case 2 Memory accesses when DMAC is inactive 10H 16 ns Case 3 Write accesses to HPIC register see Note 2 ...

Page 62: ...igh HPI write 2 ns th DSH HDV W Hold time HDx valid after DS high HPI write 3 ns tsu GPIO COH Setup time HDx input valid before CLKOUT high HDx configured as general purpose input 6 ns th GPIO COH Hold time HDx input valid after CLKOUT high HDx configured as general purpose input 0 ns DS refers to the logical OR of HCS HDS1 and HDS2 HDx refers to any of the HPI data bus pins HD0 HD1 HD2 etc GPIO r...

Page 63: ... th DSL HBV td DSH HYH tw DSL td DSL HDV1 tv HYH HDV Valid Valid Valid td COH HYH Valid tw DSH td DSH HYL th DSH HDV R th DSH HDV W Valid tsu HDV DSH td DSL HDV2 ten DSL HD HCS HDS HRDY HD READ Valid HD WRITE CLKOUT Second Byte First Byte Second Byte HAD HAD refers to HCNTL0 HCNTL1 and HR W When HAS is not used HAS always high Figure 35 Using HDS to Control Accesses HCS Always Low ...

Page 64: ...st Byte Second Byte td HCS HRDY HCS HDS HRDY Figure 36 Using HCS to Control Accesses HINT CLKOUT td COH HTX Figure 37 HINT Timing GPIOx Input Mode CLKOUT th GPIO COH GPIOx Output Mode tsu GPIO COH td COH GPIO GPIOx refers to HD0 HD1 HD2 HD7 when the HD bus is configured for general purpose input output I O Figure 38 GPIOx Timings ...

Page 65: ... 27 72 0 17 37 73 0 13 NOM 0 25 0 75 0 45 0 05 MIN 36 Seating Plane Gage Plane 108 109 144 SQ SQ 22 20 21 80 1 19 80 17 50 TYP 20 20 1 35 1 45 1 60 MAX M 0 08 0 7 0 08 0 50 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 Thermal Resistance Characteristics PARAMETER C W RΘJA 56 RΘJC 5 ...

Page 66: ... M 0 08 0 80 9 60 TYP 12 13 10 11 8 9 6 7 N M K L J H 4 2 3 F E C B D A 1 G 5 Seating Plane 4073221 2 B 08 00 SQ 11 90 12 10 0 95 0 35 0 45 0 45 0 55 0 85 0 08 0 12 1 40 MAX NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C MicroStar BGA configuration Thermal Resistance Characteristics PARAMETER C W RΘJA 38 RΘJC 5 ...

Page 67: ...ct content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for...

Page 68: ...tute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is...

Page 69: ...turing Company All Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 100 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com ...

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