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9.14.2
System Implementation of SRIO
9.15 DDR2
9.15.1
Configuration of DDR2
9.15.2
System Implementation of DDR2
9.16 JTAG/Emulation
Peripheral Section
It is possible to configure the TCI6482 to boot load application code over the SRIO interface. Boot over
SRIO is a feature that is selected using boot strapping options. For details on boot strapping options refer
to the TCI6482 data manual.
If the SRIO peripheral is not used the SRIO reference clock inputs and SRIO link pins can be left floating.
SRIO power planes can be connected to GND in order to reduce power. These power planes are:
•
DVDDRM, DVDDR, DVDD12, AVDDA, AVDDT
If the SRIO peripheral is enabled but not all links are used, the pins of unused links can be left floating
and no terminations are needed.
Refer to the Implementing Serial Rapid IO PCB Layout on a TMS320TCI6482 Hardware Design
(
SPRAAB0
for information regarding supported topologies and layout guidelines.
Suggestions on SRIO reference clocking solutions can be found in
Section 6.3.3
.
SRIO power planes and power filtering requirements are covered in
Section 7.1
.
Relevant documentation for DDR2:
•
TMS320TCI648x DSP DDR2 Memory Controller User's Guide (SPRU894)
•
Implementing DDR2 PCB Layout on the TMS320TCI6482 (
SPRAAA9
)
•
TCI6482 SRIO/DDR Example schematics
•
JEDEC JESD79-2A:
http://www.jedec.org/download/search/JESD79-2A.pdf
The DDR2 peripheral is enabled/disabled using boot strapping, as defined in the TCI6482 data manual. If
it is enabled, it still needs to be enabled via software after a reset.
The DDR2 clock is derived from PLL2, which uses the CLKIN2 reference clock. The DDR2 clock is 10x
the CLKIN2 frequency (25MHz CLKIN2 runs the DDR clock at 250MHz). The CLKIN2 range supports a
range of DDR2 operating frequencies, up to 533MHz (CLKIN2 = 26.7MHz). PLL2 is used for some of the
EMAC MII modes, specifically RMII, GMII, and RGMII. When these MII modes are selected CLKIN2 must
be 25MHz.
If the DDR2 peripheral is disabled all interface signals can be left floating since the input buffers are
disabled when the peripheral is disabled. CLKIN2 should have an external pull-down if not used. Note that
the DDR PLL voltages AVDLL1 and AVDLL2 are required to be at 1.8V even if DDR is not needed but the
filter circuit can be omitted.
If the DDR2 is operated in 16 bit mode, the upper DDR2 bi-directional pins should be pulled to valid
states. DSDDQS2, DSDDQS3, and DED[31:16] should have pull-up resistors to DVDD18. DSDDQS2z
and DSDDQS3z should have pull-downs to GND.
Refer to the Implementing DDR2 PCB Layout on the TMS320TCI6482 (
SPRAAA9
) for information
regarding supported topologies and layout guidelines.
Suggestions on CLKIN2 reference clocking solutions can be found in
Section 6.3.2
.
DDR power planes and power filtering requirements are covered in
Section 7.1
.
Relevand documentation for JTAG/Emulation:
•
60-Pin Emulation Header Technical Reference, (
SPRU655
)
•
TMS320TCI6482 BSDL file
38
TMS320TCI6482 Design Guide and Migration from TMS320TCI100
SPRAAC7B – April 2006
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