3 Silicon Revision B Usage Notes and Advisories
This section lists the usage notes and advisories for this silicon revision.
3.1 Silicon Revision B Usage Notes
This section lists all the usage notes that are applicable to silicon revision B [and earlier silicon revisions].
3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask
Clear
Revisions Affected:
0, A, B
Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state that can
trigger an unwanted interrupt. The conditions required to enter this state are:
1. A PIEACK clear is followed immediately by a global interrupt enable (EINT or asm(" CLRC INTM")).
2. A nested interrupt clears one or more PIEIER bits for its group.
Whether the unwanted interrupt is triggered depends on the configuration and timing of the other interrupts in
the system. This is expected to be a rare or nonexistent event in most applications. If it happens, the unwanted
interrupt will be the first one in the nested interrupt's PIE group, and will be triggered after the nested interrupt
re-enables CPU interrupts (EINT or asm(" CLRC INTM")).
Workaround:
Add a NOP between the PIEACK write and the CPU interrupt enable. Example code is shown
below.
//Bad interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE
EINT; //Enable nesting in the CPU
//Good interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE
asm(" NOP"); //Wait for PIEACK to exit the pipeline
EINT; //Enable nesting in the CPU
Silicon Revision B Usage Notes and Advisories
SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022
TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0
7
Copyright © 2022 Texas Instruments Incorporated
