www.ti.com
5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL)
GPIO Registers
The PIPOL determines the GPIO pin signal polarity that generates an interrupt.
The video port pin interrupt polarity register (PIPOL) is shown in
and described in
.
Figure 5-10. Video Port Pin Interrupt Polarity Register (PIPOL)
31
24
Reserved
R-0
23
22
21
20
19
18
17
16
Reserved
PIPOL22
PIPOL21
PIPOL20
PIPOL19
PIPOL18
PIPOL17
PIPOL16
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
PIPOL15
PIPOL14
PIPOL13
PIPOL12
Reserved
Reserved
PIPOL9
PIPOL8
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
PIPOL7
PIPOL6
PIPOL5
PIPOL4
PIPOL3
PIPOL2
Reserved
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-11. Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions
Bit
field
(1)
symval
(1)
Value
Description
31-23
Reserved
-
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
22
PIPOL22
OF(value)
PIPOL22 bit determines the VCTL3 pin signal polarity that generates an interrupt.
DEFAULT
0
Interrupt is caused by a low-to-high transition on the VCTL3 pin.
VCTL3ACTHI
VCTL3ACTLO
1
Interrupt is caused by a high-to-low transition on the VCTL3 pin.
21
PIPOL21
OF(value)
PIPOL21 bit determines the VCTL2 pin signal polarity that generates an interrupt.
DEFAULT
0
Interrupt is caused by a low-to-high transition on the VCTL2 pin.
VCTL2ACTHI
VCTL2ACTLO
1
Interrupt is caused by a high-to-low transition on the VCTL2 pin.
20
PIPOL20
OF(value)
PIPOL20 bit determines the VCTL1 pin signal polarity that generates an interrupt.
DEFAULT
0
Interrupt is caused by a low-to-high transition on the VCTL1 pin.
VCTL1ACTHI
VCTL1ACTLO
1
Interrupt is caused by a high-to-low transition on the VCTL1 pin.
19-2
PIPOL[19-2]
OF(value)
PIPOL[19-2] bit determines the corresponding VDATA[n] pin signal polarity that
generates an interrupt.
DEFAULT
0
Interrupt is caused by a low-to-high transition on the VDATA[n] pin.
VDATAnACTHI
VDATAnACTLO
1
Interrupt is caused by a high-to-low transition on the VDATA[n] pin.
(1)
For CSL implementation, use the notation VP_PIPOL_PIPOLn_symval.
General-Purpose I/O Operation
164
SPRUEM1 – May 2007