Texas Instruments TMS320DM357, User Manual

Page: 59 / 167

2.11.3 Debug Features
2.11.3.1 Destination FIFO Register Pointer
2.11.4 EDMA3TC Configuration
www.ti.com
EDMA3 Transfer Controller (EDMA3TC)
The DMA program register set, DMA source active register set, and the destination FIFO register set are
used to derive a brief history of TRs serviced through the transfer controller.
Additionally, the EDMA3TC status register (TCSTAT) has dedicated bit fields to indicate the ongoing
activity within different parts of the transfer controller:
•
The SRCACTV bit indicates whether the source active set is active.
•
The DSTACTV bit indicates the number of TRs resident in the destination register active set at a given
instance.
•
The PROGBUSY bit indicates whether a valid TR is present in the DMA program set.
If the TRs are in progression, caution must be used and you must realize that there is a chance that the
values read from the EDMA3TC status registers will be inconsistent since the EDMA3TC may change the
values of these registers due to ongoing activities.
It is recommended that you ensure no additional submission of TRs to the EDMA3TC in order to facilitate
ease of debug.
The destination FIFO register pointer is implemented as a circular buffer with the start pointer being
DFSTRTPTR and a buffer depth of usually 2 or 4. The EDMA3TC maintains two important status details in
TCSTAT that may be used during advanced debugging, if necessary. The DFSTRTPTR is a start pointer,
that is, the index to the head of the destination FIFO register. The DSTACTV is a counter for the number
of valid (occupied) entries. These registers may be used to get a brief history of transfers.
Examples of some register field values and their interpretation:
•
DFSTRTPTR = 0 and DSTACTV = 0 implies that no TRs are stored in the destination FIFO register.
•
DFSTRTPTR = 1 and DSTACTV = 2h implies that two TRs are present. The first pending TR is read
from the destination FIFO register entry 1 and the second pending TR is read from the destination
FIFO register entry 2.
•
DFSTRTPTR = 3h and DSTACTV = 2h implies that two TRs are present. The first pending TR is read
from the destination FIFO register entry 3 and the second pending TR is read from the destination
FIFO register entry 0.
Table 2-16 provides the configuration of the individual EDMA3 transfer controllers present on the device.
Table 2-16. EDMA3 Transfer Controller Configurations
Name TC0 TC1
FIFOSIZE 128 bytes 256 bytes
BUSWIDTH 8 bytes 8 bytes
DSTREGDEPTH 4 entries 4 entries
DBS 16 bytes 32 bytes
SPRUG34 – November 2008 EDMA3 Architecture 59
Submit Documentation Feedback