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16

1

0

CCERR

7

QEMR

1

0

EMR/EMRH

63

1

0

EDMA3CC_ERRINT

EEVAL.EVAL

pulse

Eval/

2.10 Event Queue(s)

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Event Queue(s)

Figure 2-13. Error Interrupt Operation

Event queues are a part of the EDMA3 channel controller. Event queues form the interface between the
event detection logic in the EDMA3CC and the transfer request (TR) submission logic of the EDMA3CC.
Each queue is 16 entries deep, that is, a maximum of 16 queued events per event queue. If there are
more than 16 events, then the events that cannot find a place in the event queue remain set in the
associated event register.

There are two event queues (Queue0 and Queue1) for DM357 devices. Events in Queue0 result in
submission of its associated transfer requests (TRs) to TC0. Similarly, transfer requests associated with
events in Queue1 are submitted to TC1.

An event that wins prioritization against other DMA and/or QDMA pending events is placed at the end of
the appropriate event queue. Each event queue is serviced in a FIFO (first in–first out) order. Once the
event reaches the head of its queue and the corresponding transfer controller is ready to receive another
TR, the event is dequeued and the PaRAM set corresponding to the dequeued event is processed and
submitted as a transfer request packet (TRP) to the associated EDMA3 transfer controller.

Queue0 has higher priority than Queue1, if Queue0 and Queue1 both have at least one event entry and if
both TC0 and TC1 can accept transfer requests, then the event in Queue0 is dequeued first and its
associated PaRAM set is processed and submitted as a transfer request (TR) to TC0.

See

for system-level performance considerations. All the event entries in all the event

queues are software readable (not writeable) by accessing the event entry registers (Q0E0,
Q0E1,

…

Q1E15, etc.). Each event entry register characterizes the queued event in terms of the type of

event (manual, event, chained or autotriggered) and the event number. See

Section 4.3.4.1

for a

description of the bit fields in the queue event entry registers.

SPRUG34 – November 2008

EDMA3 Architecture

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Summary of Contents for TMS320DM357

Page 1: ...TMS320DM357 DMSoC Enhanced Direct Memory Access EDMA3 Controller User s Guide Literature Number SPRUG34 November 2008 ...

Page 2: ...2 SPRUG34 November 2008 Submit Documentation Feedback ...

Page 3: ...6 Parameter Set Updates 33 2 3 7 Linking Transfers 35 2 4 Initiating a DMA Transfer 38 2 4 1 DMA Channel 38 2 4 2 QDMA Channels 41 2 4 3 Comparison Between DMA and QDMA Channels 41 2 5 Completion of a DMA Transfer 42 2 5 1 Normal Completion 43 2 5 2 Early Completion 43 2 5 3 Dummy or Null Completion 43 2 6 Event Channel and PaRAM Mapping 43 2 6 1 DMA Channel to PaRAM Mapping 44 2 6 2 QDMA Channel ...

Page 4: ...3 4 Peripheral Servicing Example 72 3 4 1 Nonbursting Peripherals 72 3 4 2 Bursting Peripherals 74 3 4 3 Continuous Operation 76 3 4 4 Ping Pong Buffering 79 3 4 5 Transfer Chaining Examples 82 4 Registers 85 4 1 Register Memory Maps 86 4 2 Parameter RAM PaRAM Entries 86 4 2 1 Channel Options Parameter OPT 87 4 2 2 Channel Source Address Parameter SRC 89 4 2 3 A Count B Count Parameter A_B_CNT 89 ...

Page 5: ... Configuration Register TCCFG 142 4 4 3 EDMA3TC Channel Status Register TCSTAT 143 4 4 4 Error Registers 144 4 4 5 Read Rate Register RDRATE 149 4 4 6 EDMA3TC Channel Registers 149 A Tips 163 A 1 Debug Checklist 163 A 2 Miscellaneous Programming Debug Tips 164 B Setting Up a Transfer 165 SPRUG34 November 2008 Contents 5 Submit Documentation Feedback ...

Page 6: ...nuous ASP Data Example Reload PaRAM 78 3 14 Ping Pong Buffering for ASP Data Example 80 3 15 Ping Pong Buffering for ASP Example PaRAM 80 3 16 Ping Pong Buffering for ASP Example Pong PaRAM 81 3 17 Ping Pong Buffering for ASP Example Ping PaRAM 82 3 18 Intermediate Transfer Completion Chaining Example 83 3 19 Single Large Block Transfer Example 84 3 20 Smaller Packet Data Transfers Example 84 4 1 ...

Page 7: ...Event Enable Set Register High EESRH 124 4 45 Secondary Event Register SER 125 4 46 Secondary Event Register High SERH 126 4 47 Secondary Event Clear Register SECR 126 4 48 Secondary Event Clear Register High SECRH 127 4 49 Interrupt Enable Register IER 128 4 50 Interrupt Enable Register High IERH 128 4 51 Interrupt Enable Clear Register IECR 129 4 52 Interrupt Enable Clear Register High IECRH 129...

Page 8: ...Source Address B Reference Register SASRCBREF 154 4 83 Source Active Destination Address B Reference Register SADSTBREF 155 4 84 Destination FIFO Options Register DFOPTn 156 4 85 Destination FIFO Source Address Register DFSRCn 157 4 86 Destination FIFO Count Register DFCNTn 158 4 87 Destination FIFO Destination Address Register DFDSTn 159 4 88 Destination FIFO B Index Register DFBIDXn 159 4 89 Des...

Page 9: ...2 4 10 EDMACC Registers 93 4 11 Peripheral ID Register PID Field Descriptions 97 4 12 EDMA3CC Configuration Register CCCFG Field Descriptions 98 4 13 QDMA Channel Map n Registers QCHMAPn Field Descriptions 99 4 14 DMA Channel Queue Number Registers DMAQNUMn Field Descriptions 100 4 15 Bits in DMAQNUMn 100 4 16 QDMA Channel Queue Number Register QDMAQNUM Field Descriptions 101 4 17 Queue Priority R...

Page 10: ...131 4 59 Interrupt Clear Register ICR Field Descriptions 132 4 60 Interrupt Clear Register High ICRH Field Descriptions 132 4 61 Interrupt Evaluate Register IEVAL Field Descriptions 133 4 62 QDMA Event Register QER Field Descriptions 134 4 63 QDMA Event Enable Register QEER Field Descriptions 135 4 64 QDMA Event Enable Clear Register QEECR Field Descriptions 136 4 65 QDMA Event Enable Set Register...

Page 11: ...s 158 4 90 Destination FIFO Destination Address Register DFDSTn Field Descriptions 159 4 91 Destination FIFO B Index Register DFBIDXn Field Descriptions 159 4 92 Destination FIFO Memory Protection Proxy Register DFMPPRXYn Field Descriptions 160 4 93 Destination FIFO Count Reload Register DFCNTRLDn Field Descriptions 161 4 94 Destination FIFO Source Address B Reference Register DFSRCBREFn Field Des...

Page 12: ...List of Tables 12 SPRUG34 November 2008 Submit Documentation Feedback ...

Page 13: ...VPBE is the video encoder on screen display and digital LCD controller SPRUG25 TMS320DM357 DMSoC ARM Subsystem Reference Guide Describes the ARM subsystem in the TMS320DM357 Digital Media System on Chip DMSoC The ARM subsystem is designed to give the ARM926EJ S ARM9 master control of the device In general the ARM is responsible for configuration and control of the device including the video proces...

Page 14: ... state of the input by reading the state of an internal register When configured as an output you can write to an internal register to control the state driven on the output pin SPRUG32 TMS320DM357 DMSoC Multimedia Card MMC Secure Digital SD Card Controller User s Guide Describes the multimedia card MMC secure digital SD card controller in the TMS320DM357 Digital Media System on Chip DMSoC The MMC...

Page 15: ... TMS320DM357 Digital Media System on Chip DMSoC video processing subsystem Included in the VPFE is the preview engine CCD controller resizer histogram and hardware 3A H3A statistic generator SPRUGH2 TMS320DM357 DMSoC Peripherals Overview Reference Guide This document provides an overview of the peripherals in the TMS320DM357 Digital Media System on Chip DMSoC SPRUGH3 TMS320DM357 DMSoC Universal Se...

Page 16: ...Read This First 16 SPRUG34 November 2008 Submit Documentation Feedback ...

Page 17: ...geometries and transfer sequences Chapter 1 provides a brief overview features and terminology Chapter 2 provides the architecture details and common operations of the EDMA3 channel controller EDMA3CC and the EDMA3 transfer controller EDMA3TC Chapter 3 contains examples and common usage scenarios Chapter 4 describes the memory mapped registers associated with the EDMA3 controller Topic Page 1 1 Ov...

Page 18: ...ts TR to the transfer controller The EDMA3 transfer controllers are slaves to the EDMA3 channel controller responsible for data movement The transfer controller issues read write commands to the source and destination addresses programmed for a given transfer The operation is transparent to you The EDMA3 channel controller has following features Fully orthogonal transfer description 3 transfer dim...

Page 19: ...evice data manual to learn more about the CPU on your system Device TMS320DM357 DMSoC DMA channel One of the 64 channels that can be triggered by external manual and chained events All DMA channels exist in the EDMA3CC Dummy set or A PaRAM set for which at least one of the count fields is equal to 0 and at least one Dummy PaRAM set of the count fields is nonzero A null PaRAM set has all the count ...

Page 20: ...channels QDMA PaRAM channels and linking Parameter RAM A 32 byte EDMA3 channel transfer definition Each parameter set consists of 8 PaRAM set words 4 bytes each which store the context for a DMA QDMA link transfer A PaRAM set includes source address destination address counts indexes options etc Parameter RAM One of the 4 byte components of the parameter set PaRAM set entry Slave end points All on...

Page 21: ...Transfer 42 2 6 Event Channel and PaRAM Mapping 43 2 7 EDMA3 Channel Controller Regions 45 2 8 Chaining EDMA3 Channels 47 2 9 EDMA3 Interrupts 49 2 10 Event Queue s 55 2 11 EDMA3 Transfer Controller EDMA3TC 57 2 12 Event Dataflow 60 2 13 EDMA3 Prioritization 61 2 14 EDMA3 Operating Frequency Clock Control 62 2 15 Reset Considerations 62 2 16 Power Management 63 2 17 Emulation Considerations 63 SPR...

Page 22: ...d submits a transfer request TR to the transfer controller EDMA3 event and interrupt processing registers Enable disable events enable disable interrupt conditions and clearing interrupts Completion detection The completion detect block detects completion of transfers by the EDMA3TC and or slave peripherals Completion of transfers can optionally be used to chain trigger new transfers or to assert ...

Page 23: ...ued in the appropriate EDMA3CC event queue The assignment of each DMA QDMA channel to event queue is programmable Each queue is 16 deep so up to 16 events may be queued on a single queue in the EDMA3CC at an instant in time Additional pending events mapped to a full queue are queued when event queue space becomes available Refer to Section 2 10 If events on different channels are detected simultan...

Page 24: ... thresholds etc For more details on error interrupts see Section 2 9 4 Figure 2 3 shows a functional block diagram of the EDMA3 transfer controller EDMA3TC The main blocks of the EDMA3TC are DMA program register set The DMA program register set stores the transfer requests received from the EDMA3 channel controller EDMA3CC DMA source active register set The DMA source active register set stores th...

Page 25: ...n For details on command fragmentation and optimization see Section 2 11 1 1 Depending on the number of entries the read controller can process up to 4 transfer requests ahead of the destination subject to the amount of free data FIFO An EDMA3 transfer is always defined in terms of three dimensions Figure 2 4 shows the three dimensions used by EDMA3 transfers These three dimensions are defined as ...

Page 26: ...ways separated by SRCBIDX and DSTBIDX as shown in Figure 2 5 where the start address of Array N is equal to the start address of Array N 1 plus source SRC or destination DST BIDX Frames are always separated by SRCCIDX and DSTCIDX For A synchronized transfers after the frame is exhausted the address is updated by adding SRCCIDX DSTCIDX to the beginning address of the last array in the frame As in F...

Page 27: ...ays separated by SRCCIDX and DSTCIDX Note that for AB synchronized transfers after a TR for the frame is submitted the address update is to add SRCCIDX DSTCIDX to the beginning address of the beginning array in the frame This is different from A synchronized transfers where the address is updated by adding SRCCIDX DSTCIDX to the start address of the last array in the frame See Section 2 3 6 for de...

Page 28: ...1C0 4040h to 01C0 405Fh Parameters for event 2 8 words 01C0 4060h to 01C0 407Fh Parameters for event 3 8 words 01C0 4080h to 01C0 409Fh Parameters for event 4 8 words 01C0 40A0h to 01C0 40BFh Parameters for event 5 8 words 01C0 40C0h to 01C0 40DFh Parameters for event 6 8 words 01C0 40E0h to 01C0 40FFh Parameters for event 7 8 words 01C0 4100h to 01C0 411Fh Parameters for event 8 8 words 01C0 4120...

Page 29: ...Rsvd DSTCIDX CCNT SRCCIDX LINK SRCBIDX DST BCNT ACNT SRC OPT PaRAM PaRAM set 0h 4h 8h Ch Byte address 1Ch 18h 14h 10h offset www ti com Parameter RAM PaRAM Each parameter set of PaRAM is organized into eight 32 bit words or 32 bytes as shown in Figure 2 7 and described in Table 2 2 Each PaRAM set consists of 16 bit and 32 bit parameters Figure 2 7 PaRAM Set SPRUG34 November 2008 EDMA3 Architecture...

Page 30: ...to 0 TR submitted for the last array in 2nd dimension Only relevant in A synchronized transfers 18h 1 SRCCIDX Source CCNT Index Signed value specifying the byte address offset between frames within a block 3rd dimension Valid values range from 32 768 and 32 767 A synchronized transfers The byte address offset from the beginning of the last source array in a frame to the beginning of the first sour...

Page 31: ...qual to 0 is considered either a null or dummy transfer A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT See Section 2 3 5 and Section 2 5 3 for details on dummy null completion conditions BCNT is a 16 bit unsigned value that specifies the number of arrays of length ACNT For normal operation valid values for BCNT are between 1 and 6...

Page 32: ...byte address offset from the beginning of the current array pointed to by SRC address to the beginning of the first source array in the next frame It applies to both A synchronized and AB synchronized transfers Note that when SRCCIDX is applied the current array in an A synchronized transfer is the last array in the frame Figure 2 5 while the current array in an AB synchronized transfer is the fir...

Page 33: ...secondary event register SER SERH or QSER bit gets cleared similar to a normal transfer Future events on that channel are serviced A dummy transfer is a legal transfer of 0 bytes See Section 4 3 5 8 and Section 4 3 2 1 for more information on the SER and EMR registers respectively There are some differences in the way the EDMA3CC logic treats a dummy versus a null transfer request A null transfer ...

Page 34: ...rays based on SRCBIDX and DSTBIDX Table 2 4 shows the details of parameter updates that occur within EDMA3CC for A synchronized and AB synchronized transfers Table 2 4 Parameter Updates in EDMA3CC for Non Null Non Dummy PaRAM Set A Synchronized Transfer AB Synchronized Transfer B Update C Update Link Update B Update C Update Link Update BCNT 1 BCNT 1 Condition BCNT 1 CCNT 1 CCNT 1 N A CCNT 1 CCNT ...

Page 35: ...can be used as a link reload parameter set The PaRAM sets associated with peripheral synchronization events see Section 2 6 should only be used for linking if the corresponding events are disabled If a PaRAM set location is mapped to a QDMA channel by QCHMAPn then copying the link PaRAM set onto the current QDMA channel PaRAM set is recognized as a trigger event and is latched in QER since a write...

Page 36: ...et 3 Null PaRAM set 0h 1CA0 4FE0h 127 Parameter set 127 c After completion of PaRAM set 127 link to null set OPT Y SRC Y BCNT Y ACNT Y DST Y SRCBIDX Y DSTBIDX Y Link Y FFFFh BCNTRLD Y CCNT Y SRCCIDX Y DSTCIDX Y Rsvd OPT Y SRC Y BCNT Y ACNT Y DST Y SRCBIDX Y DSTBIDX Y Link Y FFFFh BCNTRLD Y CCNT Y SRCCIDX Y DSTCIDX Y Rsvd PaRAM set 127 OPT Y SRC Y BCNT Y ACNT Y DST Y SRCBIDX Y DSTBIDX Y Link Y FFFF...

Page 37: ... Parameter set 126 Parameter set 0 0 01C0 4000h 01C0 4040h 01C0 4060h 01C0 4020h 2 3 1 Parameter set 1 Parameter set 2 Parameter set 3 Byte address Set PaRAM CCNT X SRCCIDX X Link 4FE0h SRCBIDX X ACNT X DSTCIDX X Rsvd BCNTRLD X DSTBIDX X DST X SRC X PaRAM set 3 OPT X 1CA0 4FE0h 127 Parameter set 127 c After completion of PaRAM set 127 link to self OPT X SRC X BCNT X ACNT X DST X SRCBIDX X DSTBIDX ...

Page 38: ... and the En bit in ER is cleared At this point a new event can be safely received by the EDMA3CC If the PaRAM set associated with the channel is a NULL set see Section 2 3 3 then no transfer request TR is submitted and the corresponding En bit in ER is cleared and simultaneously the corresponding channel bit is set in the event miss register EMR En 1 to indicate that the event was discarded due to...

Page 39: ...4 25 Unused 26 MMCRXEVT MMC SD Receive Event 27 MMCTXEVT MMC SD Transmit Event 28 I2CREVT I2C Receive Event 29 I2CXEVT I2C Transmit Event 30 31 Unused 32 GPINT0 GPIO 0 Event 33 GPINT1 GPIO 1 Event 34 GPINT2 GPIO 2 Event 35 GPINT3 GPIO 3 Event 36 GPINT4 GPIO 4 Event 37 GPINT5 GPIO 5 Event 38 GPINT6 GPIO 6 Event 39 GPINT7 GPIO 7 Event 40 GPBNKINT0 GPIO Bank 0 Event 41 GPBNKINT1 GPIO Bank 1 Event 42 ...

Page 40: ...annel When a chained completion code is detected the value of which is dictated by the transfer completion code TCC 5 0 in OPT of the PaRAM set associated with the channel it results in the corresponding bit in the chained event register CER to be set CER E TCC 1 Once a bit is set in CER the EDMA3CC prioritizes and queues the event in the appropriate event queue When the event reaches the head of ...

Page 41: ...DMA event miss register QEMR En 1 The primary difference between DMA and QDMA channels is the event channel synchronization QDMA events are either autotriggered or link triggered Autotriggering allows QDMA channels to be triggered by CPU s with a minimum number of linear writes to PaRAM Link triggering allows a linked list of transfers to be executed using a single QDMA PaRAM set and multiple link...

Page 42: ...et See Section 2 9 for details on interrupts and Section 2 8 for details on chaining You can also selectively program whether the transfer controller sends back completion codes on completion of the final transfer request TR of a parameter set TCCHEN or TCINTEN for all but the final transfer request TR of a parameter set ITCCHEN or ITCINTEN or for all TRs of a parameter set both See Section 2 8 fo...

Page 43: ...ot submit the associated transfer request to the EDMA3 transfer controller s However if the set dummy null has the OPT field programmed to return completion code intermediate final interrupt chaining completion then it will set the appropriate bits in the interrupt pending registers IPR IPRH or chained event register CER CERH The internal early completion path is used by the channel controller to ...

Page 44: ...Set 11 01C0 4160h to 01C0 417Fh DMA Channel 11 Reload QDMA PaRAM Set 12 01C0 4180h to 01C0 419Fh DMA Channel 12 Reload QDMA PaRAM Set 13 01C0 41A0h to 01C0 41BFh DMA Channel 13 Reload QDMA PaRAM Set 14 01C0 41C0h to 01C0 41DFh DMA Channel 14 Reload QDMA PaRAM Set 15 01C0 41E0h to 01C0 41FFh DMA Channel 15 Reload QDMA PaRAM Set 16 01C0 4200h to 01C0 421Fh DMA Channel 16 Reload QDMA PaRAM Set 62 01C...

Page 45: ...egion channel registers 3 Shadow region channel registers The global registers are located at a single fixed location in the EDMA3CC memory map These registers control EDMA3 resource mapping and provide debug visibility and error tracking information See the device specific data manual for the EDMA3CC memory map The channel registers including DMA QDMA and interrupt registers are accessible via th...

Page 46: ...E3 DRAE3H 01C0 2694h 01C0 2600h Access address Shadow region 3 IEVAL QSECR ER ERH Shadow region 0 QRAE0 QRAE3 EDMA3 Channel Controller Regions www ti com Table 2 8 Shadow Region Registers DRAEm DRAEHm QRAEn ER ERH QER ECR ECRH QEER ESR ESRH QEECR CER CERH QEESR EER EERH EECR EECRH EESR EESRH SER SERH SECR SECRH IER IERH IECR IECRH IESR IESRH IPR IPRH ICR ICRH Register not affected by DRAE DRAEH IE...

Page 47: ...pective region To enable a channel in a shadow region using shadow region 0 QEER writing into QEESR will not have the desired effect if the respective bit in QRAE is not set The EDMA3CC has four DMA region access registers DRAE0 3 and DRAEH0 3 and four QDMA region access registers QRAE0 3 Table 2 9 provides the shadow region and region access registers assignment to each of the EDMA3 masters Table...

Page 48: ...itted early completion or completed normal completion If intermediate transfer completion chaining ITCCHEN 1 and ITCCHEN 0 in channel m OPT is enabled the chain triggered event occurs after every intermediate transfer request of channel m is submitted early completion or completed normal completion If both final and intermediate transfer completion chaining TCCHEN 1 and ITCCHEN 1 in channel m OPT ...

Page 49: ...ration The transfer completion code TCC value is directly mapped to the bits of the interrupt pending register IPR IPRH as shown in Table 2 13 For example if TCC 10 0001b IPRH 1 is set after transfer completion and results in interrupt generation to the CPU s if the completion interrupt is enabled for the CPU See Section 2 9 1 1 for details on enabling EDMA3 transfer completion interrupts When a c...

Page 50: ...leted depending on early or normal completion Table 2 14 shows the number of interrupts occurring in different synchronized scenarios Consider channel 31 programmed with ACNT 3 BCNT 4 CCNT 5 and TCC 30 Table 2 14 Number of Interrupts Options A Synchronized AB Synchronized TCINTEN 1 ITCINTEN 0 1 Last TR 1 Last TR TCINTEN 0 ITCINTEN 1 19 All but the last TR 4 All but the last TR TCINTEN 1 ITCINTEN 1...

Page 51: ...s or EDMA3 masters in using the EDMA3 resources Transfer completion interrupts that are latched to the interrupt pending registers IPR IPRH are cleared by writing a 1 to the corresponding bit in the interrupt pending clear register ICR ICRH For example a write of 1 to ICR E0 clears a pending interrupt in IPR E0 If an incoming transfer completion code TCC gets latched to a bit in IPR IPRH then addi...

Page 52: ...in additional bits being set in IPR IPRH thereby resulting in additional interrupts It is likely that each of these bits in IPR IPRH would need different types of service therefore the ISR must check all pending interrupts and continue until all the posted interrupts are appropriately serviced Following are examples pseudo code for a CPU interrupt service routine for an EDMA3CC completion interrup...

Page 53: ...logic to reassert the interrupt pulse by setting the EVAL bit in the interrupt evaluation register IEVAL The pseudo code 1 Enter ISR 2 Read IPR IPRH 3 For the condition set in IPR IPRH that you desire to service a Service interrupt as required by application b Clear bit for serviced conditions others may still be set and other transfers may have resulted in returning the TCC to EDMA3CC after step ...

Page 54: ...serted for all EDMA3CC error conditions There are four conditions that cause the error interrupt to be pulsed DMA missed events for all 64 DMA channels These get latched in the event missed registers EMR EMRH QDMA missed events for all QDMA channels These get latched in the QDMA event missed register QEMR Threshold exceed for all event queues These get latched in EDMA3CC error register CCERR TCC e...

Page 55: ...nt queue is serviced in a FIFO first in first out order Once the event reaches the head of its queue and the corresponding transfer controller is ready to receive another TR the event is dequeued and the PaRAM set corresponding to the dequeued event is processed and submitted as a transfer request packet TRP to the associated EDMA3 transfer controller Queue0 has higher priority than Queue1 if Queu...

Page 56: ...AL number of entries starting from STRTPTR are indicative of events still queued in the respective queue The remaining entries may be read to determine which events have already been de queued and submitted to the associated transfer controller The EDMA3CC event queue includes watermarking threshold logic that allows you to keep track of maximum usage of all event queues This is useful for debuggi...

Page 57: ...ACNT array into DBS sized commands to the source destination addresses Each BCNT number of arrays are then serviced in succession Example 2 3 Command Fragmentation DBS 32 The pseudo code 1 ACNT 8 BCNT 8 SRCBIDX 8 DSTBIDX 10 SRCADDR 64 DSTADDR 191 Read Controller This is optimized from a 2D transfer to a 1D transfer such that the read side is equivalent to ACNT 64 BCNT 1 Cmd0 32 byte Cmd0 32 byte W...

Page 58: ...ly submitting commands to that slave The rate at which read commands are issued by the EDMA3TC is controlled by the RDRATE register The RDRATE register defines the number of cycles that the EDMA3TC read controller waits before issuing subsequent commands for a given TR thus minimizing the chance of the EDMA3TC consuming all available slave resources The RDRATE value should be set to a relatively s...

Page 59: ...s a circular buffer with the start pointer being DFSTRTPTR and a buffer depth of usually 2 or 4 The EDMA3TC maintains two important status details in TCSTAT that may be used during advanced debugging if necessary The DFSTRTPTR is a start pointer that is the index to the head of the destination FIFO register The DSTACTV is a counter for the number of valid occupied entries These registers may be us...

Page 60: ...CERH En ESR En ESRH En QER En bit and the SER En SERH En bit as soon as it determines the TR is non null In the case of a null set the SER En SERH En bit remains set It submits the non null non dummy TR to the associated transfer controller If the TR was programmed for early completion the EDMA3CC immediately sets the interrupt pending register IPR I TCC IPRH I TCC 32 5 If the TR was programmed fo...

Page 61: ...els transfers etc The following subsections detail various arbitration details whenever there might be occurrence of concurrent activity Figure 2 14 shows the different places EDMA3 priorities come into play The DMA event registers ER and ERH capture up to 64 events likewise the QDMA event register QER captures QDMA events for all QDMA channels therefore it is possible for events to occur simultan...

Page 62: ... available This can cause delays in submission of requests on Q1 Therefore it is recommended to reserve the higher priority Q0 TC0 for submission of urgent small real time sensitive transfers and allocate Q1 TC1 for longer nonreal time sensitive transfers Each transfer controller has a programmed system priority programmed via the QUEPRI that is implemented when multiple masters in the system are ...

Page 63: ...gic is read in TCSTAT for each EDMA3TC It is generally recommended to first disable the EDMA3CC and then the EDMA3TC s to put the EDMA3 controller in reduced power modes Additionally when EDMA3 is involved in servicing a peripheral and it is required to power down both the peripheral and the EDMA the recommended sequence is to first disable the peripheral then disable the DMA channel associated wi...

Page 64: ...EDMA3 Architecture 64 SPRUG34 November 2008 Submit Documentation Feedback ...

Page 65: ...meter configuration The following sections provides a description and PaRAM configuration for some typical use case scenarios Topic Page 3 1 Block Move Example 66 3 2 Subframe Extraction Example 68 3 3 Data Sorting Example 70 3 4 Peripheral Servicing Example 72 SPRUG34 November 2008 EDMA3 Transfer Examples 65 Submit Documentation Feedback ...

Page 66: ...transfer The source address for the transfer is set to the start of the data block in external memory and the destination address is set to the start of the data block in L2 If the data block is less than 64K bytes the PaRAM configuration in Figure 3 2 holds true with the synchronization type set to A synchronized and indexes cleared to 0 If the amount of data is greater than 64K bytes BCNT and th...

Page 67: ...ex DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0000h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0001h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 ...

Page 68: ...580h 8000 0788h 8000 0000h 1180 0000h Subframe Extraction Example www ti com The EDMA3 can efficiently extract a small frame of data from a larger frame of data By performing a 2D to 1D transfer the EDMA3 retrieves a portion of data for the CPU to process In this example a 640 480 pixel frame of video data is stored in external memory DDR2 Each pixel is represented by a 16 bit halfword The CPU ext...

Page 69: ... BCNT Index DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0000h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0001h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7...

Page 70: ...esired format Figure 3 5 shows the data sorting In order to determine the parameter entry values the following need to be considered ACNT Program this to be the size in bytes of an element BCNT Program this to be the number of elements in a frame CCNT Program this to be the number of frames SRCBIDX Program this to be the size of the element or ACNT DSTBIDX CCNT ACNT SRCCDX ACNT BCNT DSTCIDX ACNT T...

Page 71: ...ndex DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0001h 1000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0004h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 1 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 ...

Page 72: ... include the on chip audio serial port ASP and many external devices such as codecs Regardless of the peripheral the DMA channel configuration is the same The ASP transmit and receive data streams are treated independently by the EDMA3 The transmit and receive data streams can have completely different counts data sizes and formats Figure 3 7 shows servicing incoming ASP data To transfer the incom...

Page 73: ...CNT Index DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0000h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0004h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4...

Page 74: ...n external buffer one array at a time based on EVTn channel n must be configured Due to the nature of the data a video frame made up of arrays of pixels the destination is essentially a 2D entity Figure 3 10 shows the parameters to service the incoming data with a 1D to 2D transfer using AB synchronization The source address is set to the location of the video framer peripheral and the destination...

Page 75: ...tion BCNT Index DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0500h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 01E0h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10...

Page 76: ...2 and 13 must be set up for 1D to 1D transfers with A synchronization Figure 3 12 shows the parameters for the parameter entries for the channel for these transfers In order to service the ASP continuously throughout CPU operation the channels must be linked to a duplicate PaRAM set in the PaRAM After all frames have been transferred the DMA channels reload and continue Figure 3 13 shows the reloa...

Page 77: ...served TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM c EDMA Parameters for Transmit Channel PaRAM Set 2 being Linked to PaRAM Set 65 Parameter Contents Parameter 0010 1000h Channel Options Parameter OPT 1180 1000h Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for 1st Dimension ACNT 01E0 2004h Channel Destination Ad...

Page 78: ... Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM c EDMA Reload Parameters PaRAM Set 65 for Transmit Channel Parameter Contents Parameter 0010 1000h Channel Options Parameter OPT 1180 1000h Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for 1st Dimension ACNT 01E0 2004h Channel Destination Address DST 0000h 00...

Page 79: ... As soon as one transfer completes the channel loads the PaRAM set for the other and the data transfers continue Figure 3 15 shows the DMA channel configuration required Each channel has two parameter sets ping and pong The DMA channel is initially loaded with the ping parameters Figure 3 15 The link address for the ping set is set to the PaRAM offset of the pong parameter set Figure 3 16 The link...

Page 80: ...ple Figure 3 15 Ping Pong Buffering for ASP Example PaRAM a EDMA Parameters for Channel 3 Using PaRAM Set 3 Linked to Pong Set 64 Parameter Contents Parameter 0010 3000h Channel Options Parameter OPT 01E0 2000h Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for 1st Dimension ACNT 1180 0000h Channel Destination Address DST 0001h 0000h Destination BCNT Index DSTBIDX Source...

Page 81: ...A Pong Parameters for Channel 3 at Set 64 Linked to Set 65 Parameter Contents Parameter 0010 D000h Channel Options Parameter OPT 01E0 2000h Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for 1st Dimension ACNT 1180 0800h Channel Destination Address DST 0001h 0000h Destination BCNT Index DSTBIDX Source BCNT Index SRCBIDX 0080h 4820h BCNT Reload BCNTRLD Link Address LINK 0...

Page 82: ...the same rate One FIFO buffers data input and the other buffers data output The EDMA3 channels that service these FIFOs can be set up for AB synchronized transfers While each FIFO is serviced with a different set of parameters both can be signaled from a single event For example an external interrupt pin can be tied to the status flags of one of the FIFOs When this event arrives the EDMA3 needs to...

Page 83: ...1b completion interrupt Enable transfer Setup Channel 32 parameters for chaining for chaining Channel 63 parameters Enable channel 32 EERH E32 1 Event enable register EER 3 4 5 2 Breaking Up Large Transfers with Intermediate Chaining www ti com Peripheral Servicing Example Figure 3 18 Intermediate Transfer Completion Chaining Example Another feature of intermediate transfer chaining ITCCHEN is for...

Page 84: ...ys of 1 Kbyte elements for a total of 16K byte elements The TCC field in the channel options parameter OPT is set to the same value as the channel number and ITCCHEN are set In this example DMA channel 25 is used and TCC is also set to 25 The TCINTEN may also be set to trigger interrupt 25 when the last 1 Kbyte array is transferred The CPU starts the EDMA3 transfer by writing to the appropriate bi...

Page 85: ...gisters of the EDMA3 controller Topic Page 4 1 Register Memory Maps 86 4 2 Parameter RAM PaRAM Entries 86 4 3 EDMA3 Channel Controller Control Registers 93 4 4 EDMA3 Transfer Controller Control Registers 140 SPRUG34 November 2008 Registers 85 Submit Documentation Feedback ...

Page 86: ...nnel Controller EDMA3CC Parameter RAM PaRAM Entries Offset Acronym Parameter Section 0h OPT Channel Options Section 4 2 1 4h SRC Channel Source Address Section 4 2 2 8h A_B_CNT A Count B Count Section 4 2 3 Ch DST Channel Destination Address Section 4 2 4 10h SRC_DST_BIDX Source B Index Destination B Index Section 4 2 5 14h LINK_BCNTRLD Link Address B Count Reload Section 4 2 6 18h SRC_DST_CIDX So...

Page 87: ...ansfer complete chaining is enabled When enabled the chained event register CER CERH bit is set on final chained transfer completion upon completion of the final TR in the PaRAM set The bit position set in CER or CERH is the TCC value specified 21 ITCINTEN Intermediate transfer completion interrupt enable 0 Intermediate transfer complete interrupt is disabled 1 Intermediate transfer complete inter...

Page 88: ...s updated or linked after TR is submitted A value of 0 should be used for DMA channels and for nonfinal transfers in a linked list of QDMA transfers 1 PaRAM set is static PaRAM set is not updated or linked after TR is submitted A value of 1 should be used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers 2 SYNCDIM Transfer synchronization dimension 0 A synchr...

Page 89: ...rameter A_B_CNT specifies the number of bytes within the 1st dimension of a transfer and the number of arrays of length ACNT The A_B_CNT is shown in Figure 4 3 and described in Table 4 4 Figure 4 3 A Count B Count Parameter A_B_CNT 31 16 BCNT R W x 15 0 ACNT R W x LEGEND R W Read Write n value after reset x value is indeterminate after reset Table 4 4 A Count B Count Parameter A_B_CNT Field Descri...

Page 90: ... used for source address modification between each array in the 2nd dimension and the value 2s complement used for destination address modification between each array in the 2nd dimension The SRC_DST_BIDX is shown in Figure 4 5 and described in Table 4 6 Figure 4 5 Source B Index Destination B Index Parameter SRC_DST_BIDX 31 16 DSTBIDX R W x 15 0 SRCBIDX R W x LEGEND R W Read Write n value after r...

Page 91: ... W Read Write n value after reset x value is indeterminate after reset Table 4 7 Link Address B Count Reload Parameter LINK_BCNTRLD Field Descriptions Bit Field Value Description 31 16 BCNTRLD 0 FFFFh B count reload The count value used to reload BCNT in the A count B count parameter A_B_CNT when BCNT decrements to 0 TR submitted for the last array in 2nd dimension Only relevant in A synchronized ...

Page 92: ... Description 31 16 DSTCIDX 0 FFFFh Destination C index Signed value specifying the byte address offset between frames within a block 3rd dimension Valid values range from 32 768 and 32 767 15 0 SRCCIDX 0 FFFFh Source C index Signed value specifying the byte address offset between frames within a block 3rd dimension Valid values range from 32 768 and 32 767 The C count parameter CCNT specifies the ...

Page 93: ...Number Register 5 Section 4 3 1 4 0258h DMAQNUM6 DMA Queue Number Register 6 Section 4 3 1 4 025Ch DMAQNUM7 DMA Queue Number Register 7 Section 4 3 1 4 0260h QDMAQNUM QDMA Queue Number Register Section 4 3 1 5 0284h QUEPRI Queue Priority Register Section 4 3 1 6 0300h EMR Event Missed Register Section 4 3 2 1 0304h EMRH Event Missed Register High Section 4 3 2 1 0308h EMCR Event Missed Clear Regis...

Page 94: ...le Set Register High Section 4 3 5 7 1038h SER Secondary Event Register Section 4 3 5 8 103Ch SERH Secondary Event Register High Section 4 3 5 8 1040h SECR Secondary Event Clear Register Section 4 3 5 9 1044h SECRH Secondary Event Clear Register High Section 4 3 5 9 1050h IER Interrupt Enable Register Section 4 3 6 1 1054h IERH Interrupt Enable Register High Section 4 3 6 1 1058h IECR Interrupt En...

Page 95: ...h 2060h IESR Interrupt Enable Set Register 2064h IESRH Interrupt Enable Set Register High 2068h IPR Interrupt Pending Register 206Ch IPRH Interrupt Pending Register High 2070h ICR Interrupt Clear Register 2074h ICRH Interrupt Clear Register High 2078h IEVAL Interrupt Evaluate Register 2080h QER QDMA Event Register 2084h QEER QDMA Event Enable Register 2088h QEECR QDMA Event Enable Clear Register 2...

Page 96: ...2260h IESR Interrupt Enable Set Register 2264h IESRH Interrupt Enable Set Register High 2268h IPR Interrupt Pending Register 226Ch IPRH Interrupt Pending Register High 2270h ICR Interrupt Clear Register 2274h ICRH Interrupt Clear Register High 2278h IEVAL Interrupt Evaluate Register 2280h QER QDMA Event Register 2284h QEER QDMA Event Enable Register 2288h QEECR QDMA Event Enable Clear Register 228...

Page 97: ... PID Peripheral identifier 4001 1B00h Uniquely identifies the EDMA3CC and the specific revision of the EDMA3CC The EDMA3CC configuration register CCCFG provides the features resources for the EDMA3CC in a particular device The CCCFG is shown in Figure 4 10 and described in Table 4 12 Figure 4 10 EDMA3CC Configuration Register CCCFG 31 26 25 24 Reserved MP_EXIST CHMAP_EXIST R x R 0 R 0 23 22 21 20 ...

Page 98: ... 0 3h Number of shadow regions 0 1 Reserved 2h 4 regions 3h Reserved 19 Reserved 0 Reserved 18 16 NUM_EVQUE 0 7h Number of queues number of TCs 0 Reserved 1 2 EDMA3TC Event Queues 2h 7h Reserved 15 Reserved 0 Reserved 14 12 NUM_PAENTRY 0 7h Number of PaRAM sets 0 2h Reserved 3h 128 sets 4h 7h Reserved 11 Reserved 0 Reserved 10 8 NUM_INTCH 0 7h Number of interrupt channels 0 3h Reserved 4h 64 inter...

Page 99: ...QCHMAPn should be programmed appropriately to point to a different PaRAM set Figure 4 11 QDMA Channel Map n Registers QCHMAPn 31 16 Reserved R 0 15 14 13 5 4 2 1 0 Reserved PAENTRY TRWORD Reserved R 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 4 13 QDMA Channel Map n Registers QCHMAPn Field Descriptions Bit Field Value Description 31 14 Reserved 0 Reserved 13 5 PAE...

Page 100: ... 24 23 22 20 19 18 16 Rsvd En Rsvd En Rsvd En Rsvd En R 0 R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 15 14 12 11 10 8 7 6 4 3 2 0 Rsvd En Rsvd En Rsvd En Rsvd En R 0 R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 14 DMA Channel Queue Number Registers DMAQNUMn Field Descriptions Bit Field Value Description 31 0 En 0 7h DMA queue number Contains the event ...

Page 101: ...M 31 30 28 27 26 24 23 22 20 19 18 16 Rsvd E7 Rsvd E6 Rsvd E5 Rsvd E4 R 0 R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 15 14 12 11 10 8 7 6 4 3 2 0 Rsvd E3 Rsvd E2 Rsvd E1 Rsvd E0 R 0 R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 16 QDMA Channel Queue Number Register QDMAQNUM Field Descriptions Bit Field Value Description 31 0 En 0 7h QDMA queue number Co...

Page 102: ...ity 3 Reserved 0 Reserved 2 0 PRIQ0 0 7h Priority level for queue 0 Dictates the priority level used by TC0 relative to other masters in the device A value of 0 means highest priority and a value of 7 means lowest priority The EDMA3CC contains a set of registers that provide information on missed DMA and or QDMA events and instances when event queue thresholds are exceeded If any of the bits in th...

Page 103: ...n the event missed clear register EMCR 0 No missed event 1 Missed event occurred Figure 4 16 Event Missed Register High EMRH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E...

Page 104: ...ter reset Table 4 20 Event Missed Clear Register EMCR Field Descriptions Bit Field Value Description 31 0 En Event missed 0 31 clear All error bits must be cleared before additional error interrupts will be asserted by the EDMA3CC 0 No effect 1 Corresponding missed event bit in the event missed register EMR is cleared En 0 Figure 4 18 Event Missed Clear Register High EMCRH 31 30 29 28 27 26 25 24 ...

Page 105: ...eared the EDMA3CC generates an error interrupt Refer to Section 2 9 4 for details on EDMA3CC error interrupt generation The QEMR is shown in Figure 4 19 and described in Table 4 22 Figure 4 19 QDMA Event Missed Register QEMR 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 4 22 QDMA Event Misse...

Page 106: ...20 and described in Table 4 23 Figure 4 20 QDMA Event Missed Clear Register QEMCR 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 4 23 QDMA Event Missed Clear Register QEMCR Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 En QDMA event missed clear All error bits m...

Page 107: ... CCERRCLR The CCERR is shown in Figure 4 21 and described in Table 4 24 Figure 4 21 EDMA3CC Error Register CCERR 31 17 16 Reserved TCCERR R 0 R 0 15 2 1 0 Reserved QTHRXCD1 QTHRXCD0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 4 24 EDMA3CC Error Register CCERR Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 TCCERR Transfer completion code error TCCERR is cle...

Page 108: ... W 0 15 2 1 0 Reserved QTHRXCD1 QTHRXCD0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 4 25 EDMA3CC Error Clear Register CCERRCLR Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 TCCERR Transfer completion code error clear 0 No effect 1 Clears the TCCERR bit in the EDMA3CC error register CCERR 15 2 Reserved 0 Reserved 1 QTHRXCD1 Queue threshold error clear fo...

Page 109: ...quent error conditions Writes of 0 have no effect The EEVAL is shown in Figure 4 23 and described in Table 4 26 Figure 4 23 Error Evaluation Register EEVAL 31 16 Reserved R 0 15 2 1 0 Reserved Rsvd EVAL R 0 R W 0 W 0 LEGEND R W Read Write R Read only W Write only n value after reset Table 4 26 Error Evaluation Register EEVAL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1...

Page 110: ...W 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 LEGEND R W Read Write n value after reset Figure 4 25 DMA Region Access Enable High Register for Region m DRAEHm 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E63 E62 E61 E60 E59 E58 E57 ...

Page 111: ... 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 LEGEND R W Read Write R Read only n value after reset Table 4 28 QDMA Region Access Enable for Region m QRAEm Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 En QDMA region access enable for bit n QDMA channel n in region m 0 Accesses via region m address space to bit n in any QDMA channel r...

Page 112: ...PE For example if the value in Q1E4 is read as 000 004Fh this means the 4th entry in queue 1 is a manually triggered event on DMA channel 15 The QxEy is shown in Figure 4 27 and described in Table 4 29 Figure 4 27 Event Queue Entry Registers QxEy 31 16 Reserved R 0 15 8 7 6 5 0 Reserved ETYPE ENUM R 0 R x R x LEGEND R Read only n value after reset x value is indeterminate after reset Table 4 29 Ev...

Page 113: ...d 1 Threshold specified by the Qn bit in the queue watermark threshold A register QWMTHRA has been exceeded 23 21 Reserved 0 Reserved 20 16 WM 0 1Fh Watermark for maximum queue usage Watermark tracks the most entries that have been in queue n since reset or since the last time that the watermark WM bit was cleared WM is cleared by writing a 1 to the corresponding QTHRXCDn bit in the EDMA3CC error ...

Page 114: ...DMA3CC error register CCERR and the THRXCD bit in the queue status register 1 QSTAT1 are set when the number of events in queue 1 at an instant in time visible via the NUMVAL bit in QSTAT1 equals or exceeds the value specified by Q1 0 10h The default is 16 maximum allowed 11h Disables the threshold errors 12h 1Fh Reserved 7 5 Reserved 0 Reserved 4 0 Q0 0 1Fh Queue threshold for queue 0 value The Q...

Page 115: ...ued in queue 0 15 14 Reserved 0 Reserved 13 8 COMPACTV 0 3Fh Completion request active The COMPACTV field reflects the count for the number of completion requests submitted to the transfer controllers This count increments every time a TR is submitted and is programmed to report completion the TCINTEN or TCCCHEN bits in OPT in the parameter entry associated with the TR are set to 1 The counter dec...

Page 116: ...They are also accessible via read writes to the shadow address range The read write ability to the registers in the shadow region are controlled by the DMA region access registers DRAEm DRAEHm The registers are described in Section 4 3 3 1 and the details for shadow region global region usage is explained in Section 2 7 All external events are captured in the event register ER ERH The events are l...

Page 117: ...prioritized versus other pending DMA QDMA events for submission to the EDMA3TC Figure 4 32 Event Register High ERH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32 R 0 R 0...

Page 118: ... 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 4 35 Event Clear Register ECR Field Descriptions Bit Field Value Description 31 0 En Event clear for event 0 31 Any of the event bits in ECR is set to 1 to clear the event En in the e...

Page 119: ...ly set then EMR EMRH would be set since an event is lost If the event was previously clear then the event remains set and is prioritized for submission to the event queues Manually triggered transfers via writes to ESR ESRH allow the CPU to submit DMA requests in the system these are relevant for memory to memory transfer scenarios If the ESR En ESRH En bit is already set and another CPU write of ...

Page 120: ...fer request submission to the transfer controllers This results in a chained triggered transfer The chained event registers do not have any enables The generation of a chained event is essentially enabled by the PaRAM entry that has been configured for intermediate and or final chaining on transfer completion The En bit is set regardless of the state of EER En EERH En when a chained completion cod...

Page 121: ...is prioritized versus other pending DMA QDMA events for submission to the EDMA3TC Figure 4 38 Chained Event Register High CERH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33...

Page 122: ...Table 4 42 Figure 4 39 Event Enable Register EER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only ...

Page 123: ...able 4 44 Figure 4 41 Event Enable Clear Register EECR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND W Writ...

Page 124: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 4 45 Event Enable Set ...

Page 125: ... the EDMA3CC to evaluate subsequent events and perform subsequent transfers on the same channel Based on whether the associated TR is valid or it is a null or dummy TR the implications on the state of SER SERH and the required user action in order to submit another DMA transfer might be different The SER is shown in Figure 4 45 and described in Table 4 47 The SERH is shown in Figure 4 46 and descr...

Page 126: ...ation logic will not prioritize additional events The secondary event clear registers SECR SECRH clear the status of the secondary event registers SER SERH CPU writes of 1 clear the corresponding set bits in SER SERH Writes of 0 have no effect The SECR is shown in Figure 4 47 and described in Table 4 49 The SECRH is shown in Figure 4 48 and described in Table 4 50 Figure 4 47 Secondary Event Clear...

Page 127: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 4 50 Secondary Event Clear Register High SECRH Field Descriptions Bit Field Value Description 31 0 En Secondary event clear register 0 No effect 1 Corresponding bit in the secondary event register...

Page 128: ... in Table 4 52 Figure 4 49 Interrupt Enable Register IER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I31 I30 I29 I28 I27I I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R R...

Page 129: ...0 W 0 W 0 LEGEND W Write only n value after reset Table 4 53 Interrupt Enable Clear Register IECR Field Descriptions Bit Field Value Description 31 0 En Interrupt enable clear for channels 0 31 0 No effect 1 Corresponding bit in the interrupt enable register IER is cleared In 0 Figure 4 52 Interrupt Enable Clear Register High IECRH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I63 I62 I61 I60 I5...

Page 130: ... W 0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 4 55 Interrupt Enable Set Register IESR Field Descriptions Bit Field Value Description 31 0 En Interrupt enable set for channels 0 31 0 No effect 1 Corresponding bit in the interrupt enable register IER is set In 1 Figure 4 54 Interrupt Enable Set Register High IESRH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I63 I62 I61 I60 I59 I...

Page 131: ...16 I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 4 57 Interrupt Pending Register IPR Field Descriptions Bit Field Val...

Page 132: ...0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 4 59 Interrupt Clear Register ICR Field Descriptions Bit Field Value Description 31 0 In Interrupt clear register for TCC 0 31 0 No effect 1 Corresponding bit in the interrupt pending register IPR is cleared In 0 Figure 4 58 Interrupt Clear Register High ICRH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 133: ...svd EVAL R 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 4 61 Interrupt Evaluate Register IEVAL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 0 EVAL Interrupt evaluate 0 No effect 1 Causes EDMA3CC completio...

Page 134: ...orresponding QDMA event auto trigger is evaluated by the EDMA3CC logic for an associated transfer request submission to the transfer controllers The setting of an event is a higher priority relative to clear operations via hardware If set and clear conditions occur concurrently the set condition wins If the event was previously set then the QDMA event missed register QEMR would be set because an e...

Page 135: ...ch any event for a QDMA channel if it is not enabled via QEER The QEER is shown in Figure 4 61 and described in Table 4 63 Figure 4 61 QDMA Event Enable Register QEER 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 4 63 QDMA Event Enable Register QEER Field Descriptions Bit Field Value Descrip...

Page 136: ... QEER writes of 0 have no effect The QEECR is shown in Figure 4 62 and described in Table 4 64 Figure 4 62 QDMA Event Enable Clear Register QEECR 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 4 64 QDMA Event Enable Clear Register QEECR Field Descriptions Bit Field Value Descript...

Page 137: ...in QEER writes of 0 have no effect The QEESR is shown in Figure 4 63 and described in Table 4 65 Figure 4 63 QDMA Event Enable Set Register QEESR 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 4 65 QDMA Event Enable Set Register QEESR Field Descriptions Bit Field Value Descriptio...

Page 138: ...on the channel Based on whether the associated TR is valid or it is a null or dummy TR the implications on the state of QSER and the required user action in order to submit another QDMA transfer might be different The QSER is shown in Figure 4 64 and described in Table 4 66 Figure 4 64 QDMA Secondary Event Register QSER 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 R...

Page 139: ...ot affect the event registers The QSECR is shown in Figure 4 65 and described in Table 4 67 Figure 4 65 QDMA Secondary Event Clear Register QSECR 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 4 67 QDMA Secondary Event Clear Register QSECR Field Descriptions Bit Field Value Descr...

Page 140: ...ss B Reference Register Section 4 4 6 9 0280h DFCNTRLD Destination FIFO Set Count Reload Section 4 4 6 16 0284h DFSRCBREF Destination FIFO Set Destination Address B Reference Register Section 4 4 6 17 0288h DFDSTBREF Destination FIFO Set Destination Address B Reference Register Section 4 4 6 18 0300h DFOPT0 Destination FIFO Options Register 0 Section 4 4 6 10 0304h DFSRC0 Destination FIFO Source A...

Page 141: ... FIFO Memory Protection Proxy Register 3 Section 4 4 6 15 The peripheral identification register PID is a constant register that uniquely identifies the EDMA3TC and specific revision of the EDMA3TC The PID is shown in Figure 4 66 and described in Table 4 69 Figure 4 66 Peripheral ID Register PID 31 16 PID R 0333h 15 0 PID R 4425h LEGEND R Read only n value after reset Table 4 69 Peripheral ID Regi...

Page 142: ...t x value is indeterminate after reset Table 4 70 EDMA3TC Configuration Register TCCFG Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 8 DREGDEPTH 0 3h Destination register FIFO depth parameterization 0 1h Reserved 2h 4 entry for TC0 and TC1 3h Reserved 7 6 Reserved 0 Reserved 5 4 BUSWIDTH 0 3h Bus width parameterization 0 Reserved 1h 64 bit for TC0 and TC1 2h 3h Reserve...

Page 143: ...contains 2 TR 3h Destination FIFO contains 3 TR 4h Destination FIFO contains 4 TR Full if DSTREGDEPTH 4 If the destination register FIFO is empty then any TR written to Prog Set immediately transitions to the destination register FIFO If the destination register FIFO is not empty and not full then any TR written to Prog Set immediately transitions to the destination register FIFO set if the source...

Page 144: ...lue Description 31 4 Reserved 0 Reserved 3 MMRAERR MMR address error 0 Condition is not detected 1 User attempted to read or write to an invalid address in configuration memory map 2 TRERR Transfer request TR error event 0 Condition is not detected 1 TR detected that violates constant addressing mode transfer SAM or DAM is set to 1 alignment rules or has ACNT or BCNT 0 1 Reserved 0 Reserved 0 BUSE...

Page 145: ... Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 MMRAERR Interrupt enable for MMR address error MMRAERR 0 MMRAERR is disabled 1 MMRAERR is enabled and contributes to the state of EDMA3TC error interrupt generation 2 TRERR Interrupt enable for transfer request error TRERR 0 TRERR is disabled 1 TRERR is enabled and contributes to the state of EDMA3TC error interrupt generation 1 ...

Page 146: ...erved 0 Reserved 3 MMRAERR Interrupt enable clear for the MMRAERR bit in the error status register ERRSTAT 0 No effect 1 Clears the MMRAERR bit in ERRSTAT but does not clear the error details register ERRDET 2 TRERR Interrupt enable clear for the TRERR bit in the error status register ERRSTAT 0 No effect 1 Clears the TRERR bit in ERRSTAT but does not clear the error details register ERRDET 1 Reser...

Page 147: ...n an error 16 TCINTEN 0 1 Transfer completion interrupt enable Contains the TCINTEN value in the channel options parameter OPT programmed by the channel controller for the read or write transaction that resulted in an error 15 14 Reserved 0 Reserved 13 8 TCC 0 3Fh Transfer complete code Contains the TCC value in the channel options parameter OPT programmed by the channel controller for the read or...

Page 148: ...0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 4 76 Error Interrupt Command Register ERRCMD Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 Reserved 0 Reserved Writes of 1 to this bit are not supported Attempts to do so may result in undefined behavior 0 EVAL Error evaluate 0 No effect 1 EDMA3TC error line is pulsed if any of the error status register...

Page 149: ...y Figure 4 74 Read Rate Register RDRATE 31 16 Reserved R 0 15 3 2 0 Reserved RDRATE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 77 Read Rate Register RDRATE Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 RDRATE 0 7h Read rate Controls the number of cycles between read commands This is a global setting that applies to all TRs for this EDMA3TC...

Page 150: ...C 0 3Fh Transfer complete code This 6 bit code is used to set the relevant bit in CER or IPR of the EDMA3PCC module 11 Reserved 0 Reserved 10 8 FWID 0 7h FIFO width Applies if either SAM or DAM is set to constant addressing mode 0 FIFO width is 8 bits 1h FIFO width is 16 bits 2h FIFO width is 32 bits 3h FIFO width is 64 bits 4h FIFO width is 128 bits 5h FIFO width is 256 bits 6h 7h Reserved 7 Rese...

Page 151: ...ctive count register SACNT is shown in Figure 4 77 and described in Table 4 80 Figure 4 77 Source Active Count Register SACNT 31 16 BCNT R 0 15 0 ACNT R 0 LEGEND R Read only n value after reset Table 4 80 Source Active Count Register SACNT Field Descriptions Bit Field Value Description 31 16 BCNT 0 FFFFh B dimension count Number of arrays to be transferred where each array is ACNT in length It is ...

Page 152: ...ys reads as 0 The source active set B dimension index register SABIDX is shown in Figure 4 79 and described in Table 4 82 Figure 4 79 Source Active Source B Dimension Index Register SABIDX 31 16 DSTBIDX R 0 15 0 SRCBIDX R 0 LEGEND R Read only n value after reset Table 4 82 Source Active Source B Dimension Index Register SABIDX Field Descriptions Bit Field Value Description 31 16 DSTBIDX 0 B Index ...

Page 153: ...d is set up when the associated TR is submitted to the EDMA3TC The privilege ID is used while issuing read and write command to the target endpoints so that the target endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA transaction 0 User level privilege 1 Supervisor level privilege 7 4 Reserved 0 Reserved 3 0 PRIVID 0 Fh Privilege ID This contains the ...

Page 154: ...eserved 15 0 ACNTRLD 0 FFFFh A count reload value Represents the originally programmed value of ACNT The reload value is used to reinitialize ACNT after each array is serviced The source active source address B reference register SASRCBREF is shown in Figure 4 82 and described in Table 4 85 Figure 4 82 Source Active Source Address B Reference Register SASRCBREF 31 16 SADDRBREF R 0 15 0 SADDRBREF R...

Page 155: ...re 4 83 and described in Table 4 86 Figure 4 83 Source Active Destination Address B Reference Register SADSTBREF 31 16 DADDRBREF R 0 15 0 DADDRBREF R 0 LEGEND R Read only n value after reset Table 4 86 Source Active Destination Address B Reference Register SADSTBREF Field Descriptions Bit Field Value Description 31 0 DADDRBREF 0 Always reads as 0 SPRUG34 November 2008 Registers 155 Submit Document...

Page 156: ...21 Reserved 0 Reserved 20 TCINTEN Transfer complete interrupt enable 0 Transfer complete interrupt is disabled 1 Transfer complete interrupt is enabled 19 18 Reserved 0 Reserved 17 12 TCC 0 3Fh Transfer complete code This 6 bit code is used to set the relevant bit in CER or IPR of the EDMA3PCC module 11 Reserved 0 Reserved 10 8 FWID 0 7h FIFO width Applies if either SAM or DAM is set to constant a...

Page 157: ...addressing within an array wraps around upon reaching FIFO width The destination FIFO source address register DFSRCn is shown in Figure 4 85 and described in Table 4 88 Note The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC Figure 4 85 Destination FIFO Source Address Register DFSRCn 31 16 SADDR R 0 15 0 SADDR R 0 LEGEND R Read only n value after reset Table 4 88 Destination FIFO S...

Page 158: ...fter reset Table 4 89 Destination FIFO Count Register DFCNTn Field Descriptions Bit Field Value Description 31 16 BCNT 0 FFFFh B dimension count Number of arrays to be transferred where each array is ACNT in length Count count remaining for destination register set Represents the amount of data remaining to be written 15 0 ACNT 0 FFFFh A dimension count Number of bytes to be transferred in first d...

Page 159: ... Destination address for the destination FIFO register set When a transfer request TR is complete the final value should be the address of the last write command issued The destination FIFO B index register DFBIDXn is shown in Figure 4 88 and described in Table 4 91 Note The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC Figure 4 88 Destination FIFO B Index Register DFBIDXn 31 16 D...

Page 160: ...oller This field is set up when the associated TR is submitted to the EDMA3TC The privilege ID is used while issuing read and write command to the target endpoints so that the target endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA transaction 0 User level privilege 1 Supervisor level privilege 7 4 Reserved 0 Reserved 3 0 PRIVID 0 Fh Privilege ID Thi...

Page 161: ...lue Description 31 16 Reserved 0 Reserved 15 0 ACNTRLD 0 FFFFh A count reload value Represents the originally programmed value of ACNT The reload value is used to reinitialize ACNT after each array is serviced The destination FIFO source address B reference register DFSRCBREFn is shown in Figure 4 91 and described in Table 4 94 Figure 4 91 Destination FIFO Source Address B Reference Register DFSRC...

Page 162: ...ination Address B Reference Register DFDSTBREFn 31 16 DADDRBREF R 0 15 0 DADDRBREF R 0 LEGEND R Read only n value after reset Table 4 95 Destination FIFO Destination Address B Reference Register DFDSTBREFn Field Descriptions Bit Field Value Description 31 0 DADDRBREF 0 FFFF FFFFh Destination address reference for the destination FIFO register set Represents the starting address for the array curre...

Page 163: ...ically if the parameter set is nonstatic and expected to be terminated by a NULL set OPT STATIC 0 LINK FFFFh the parameter set is updated with a NULL set after submission of the last TR Because QDMA channels are autotriggered this update caused the generation of an event An event generated for a NULL set causes an error condition and results in setting the bits corresponding to the QDMA channel in...

Page 164: ... by region access enable registers DRAE DRAEH QRAE If the appropriate channels are not enabled in these registers read write access to the shadow region memory map is not enabled 3 When working with shadow region completion interrupts ensure that the DMA region access enable registers DRAE DRAEH for every region are set in a mutually exclusive way unless it is a requirement for an application If t...

Page 165: ... Parameter set setup Program the PaRAM set number associated with the channel Note that if it is a QDMA channel the PaRAM entry that is configured as trigger word is written last Alternatively enable the QDMA channel just before the write to the trigger word See Chapter 3 for parameter set field setups for different types of transfers See the sections on chaining Section 2 8 and interrupt completi...

Page 166: ... bits must be cleared in IPR IPRH by writing to the corresponding bit in ICR ICRH b If polling for completion interrupts not enabled in the device controller then the application code can wait on the expected bits to be set in IPR IPRH Again the set bits in IPR IPRH must be manually cleared by writing to ICR ICRH before the next set of transfers is performed for the same transfer completion code v...

Page 167: ...usiness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all neces...

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