Texas Instruments TMS320DM357, User Manual

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4.4.5 Read Rate Register (RDRATE)
4.4.6 EDMA3TC Channel Registers
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EDMA3 Transfer Controller Control Registers
The EDMA3 transfer controller issues read commands at a rate controlled by the read rate register
(RDRATE). The RDRATE defines the number of idle cycles that the read controller must wait before
issuing subsequent commands. This applies both to commands within a transfer request packet (TRP)
and for commands that are issued for different transfer requests (TRs). For instance, if RDRATE is set to
4 cycles between reads, there are 3 inactive cycles between reads.
RDRATE allows flexibility in transfer controller access requests to an endpoint. For an application,
RDRATE can be manipulated to slow down the access rate, so that the endpoint may service requests
from other masters during the inactive EDMA3TC cycles.
The RDRATE is shown in Figure 4-74 and described in Table 4-77 .
Note: It is expected that the RDRATE value for a transfer controller is static, as it is decided based
on the application requirement. It is not recommended to change this setting on the fly.
Figure 4-74. Read Rate Register (RDRATE)
31 16
Reserved
R-0
15 3 2 0
Reserved RDRATE
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 4-77. Read Rate Register (RDRATE) Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reserved
2-0 RDRATE 0-7h Read rate. Controls the number of cycles between read commands. This is a global setting that applies
to all TRs for this EDMA3TC.
0 Reads issued as fast as possible.
1h 4 cycles between reads.
2h 8 cycles between reads.
3h 16 cycles between reads.
4h 32 cycles between reads.
5h-7h Reserved
The EDMA3TC channel registers are split into three parts: the programming registers, the source active
registers, and the destination FIFO register. This section describes the registers and their functions. The
program register set is programmed by the channel controller, and is for internal use. The other two sets
are read-only and provided to facilitate advanced debug capabilities. The number of destination FIFO
register sets depends on the destination FIFO depth.
Both TC0 and TC1 have a destination FIFO depth of 4, and there are four sets of destination FIFO
registers. The number of destination FIFO register sets depends on the destination FIFO depth.
SPRUG34 – November 2008 Registers 149
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