Texas Instruments TMS320DM357, User Manual

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4.4.3 EDMA3TC Channel Status Register (TCSTAT)
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EDMA3 Transfer Controller Control Registers
The EDMA3TC channel status register (TCSTAT) is shown in Figure 4-68 and described in Table 4-71 .
Figure 4-68. EDMA3TC Channel Status Register (TCSTAT)
31 16
Reserved
R-0
15 13 12 11 10 9 8
Reserved DFSTRTPTR Reserved Reserved
R-0 R-0 R-0 R-1
7 6 4 3 2 1 0
Reserved DSTACTV Reserved WSACTV SRCACTV PROGBUSY
R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 4-71. EDMA3TC Channel Status Register (TCSTAT) Field Descriptions
Bit Field Value Description
31-13 Reserved 0 Reserved
12-11 DFSTRTPTR 0-3h Destination FIFO start pointer. The offset to the head entry of the destination register FIFO, in units of
*entries*.
10-9 Reserved 0 Reserved
8 Reserved 1 Reserved. Always read as 1.
7 Reserved 0 Reserved
6-4 DSTACTV 0-7h Destination active state. Specifies the number of transfer requests (TRs) that are resident in the
destination register FIFO at a given instant. This bit field can be primarily used for advanced debugging.
0 Destination FIFO is empty.
1h Destination FIFO contains 1 TR.
2h Destination FIFO contains 2 TR.
3h Destination FIFO contains 3 TR.
4h Destination FIFO contains 4 TR. (Full if DSTREGDEPTH == 4)
If the destination register FIFO is empty, then any TR written to Prog Set immediately transitions to the
destination register FIFO. If the destination register FIFO is not empty and not full, then any TR written
to Prog Set immediately transitions to the destination register FIFO set if the source active state
(SRCACTV) bit is set to idle.
If the destination register FIFO is full, then TRs cannot transition to the destination register FIFO. The
destination register FIFO becomes not full when the TR at the head of the destination register FIFO is
completed.
5h-7h Reserved
3 Reserved 0 Reserved
2 WSACTV Write status active.
0 Write status is not pending. Write status has been received for all previously issued write commands.
1 Write status is pending. Write status has not been received for all previously issued write commands.
1 SRCACTV Source active state.
0 Source controller is idle. Source active register set contains a previously processed transfer request.
1 Source controller is busy servicing a transfer request.
0 PROGBUSY Program register set busy.
0 Program set idle and is available for programming by the EDMA3CC.
1 Program set busy.
SPRUG34 – November 2008 Registers 143
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