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6.6.16 Clock Status Register (CKSTAT)

PLL Controller Register Map

The clock status (CKSTAT) register is shown in

Figure 6-18

and described in

Table 6-19

for PLLC1 and

PLLC2. CKSTAT shows the on/off status of the bypass clock (SYSCLKBP) and the auxiliary clock
(AUXCLK). PLLC2 does not use the auxiliary clock, so the AUXEN bit field is reserved for PLLC2.

Figure 6-18. Clock Status Register (CKSTAT)

Reserved

R-0

Reserved

BPON

Reserved

AUXEN

R-0

R-1

R-0

R-1

R-0

R-1

R-0

LEGEND: R = Read only; -n = value after reset

Table 6-19. Clock Status Register (CKSTAT) Field Descriptions

Bit

Field

Value

Description

31-4

Reserved

BPON

SYSCLKBP status. Shows the clock on/off status for SYSCLKBP.

Bypass clock is off

Bypass clock is on

2-1

Reserved

AUXEN

AUXCLK status. Shows the clock on/off status for AUXCLK.

Aux clock is off

Aux clock is on

PLL Controllers (PLLCs)

SPRUFB3 – September 2007

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Summary of Contents for TMS320DM355

Page 1: ...TMS320DM355 Digital Media System on Chip DMSoC ARM Subsystem User s Guide Literature Number SPRUFB3 September 2007 ...

Page 2: ...2 SPRUFB3 September 2007 Submit Documentation Feedback ...

Page 3: ...m 23 3 6 2 Memory Management Unit 24 3 6 3 Caches and Write Buffer 25 3 7 Tightly Coupled Memory 26 3 8 Embedded Trace Support 27 4 Memory Mapping 29 4 1 Memory Map 29 4 1 1 ARM Internal Memories 30 4 1 2 External Memories 30 4 1 3 MPEG JPEG Coprocessor MJCP 31 4 1 4 Peripherals 31 4 2 Memory Interfaces Overview 33 4 2 1 DDR2 EMIF 33 4 2 2 External Memory Interface 33 5 Device Clocking 35 5 1 Over...

Page 4: ...Register DCHANGE 58 6 6 15 Clock Enable Control Register CKEN 59 6 6 16 Clock Status Register CKSTAT 60 6 6 17 SYSCLK Status Register SYSTAT 61 6 6 18 PLL Controller Divider 4 Register PLLDIV4 62 7 Power and Sleep Controller 63 7 1 Introduction 63 7 2 DM355 Power Domain and Module Topolgy 63 7 3 Power Domain and Module States Defined 66 7 3 1 Power Domain States 66 7 3 2 Module States 66 7 4 Execu...

Page 5: ...egister 0 IRQ0 96 8 4 4 Interrupt Request Status Register 1 IRQ1 97 8 4 5 Fast Interrupt Request Entry Address Register FIQENTRY 98 8 4 6 Interrupt Request Entry Address Register IRQENTRY 99 8 4 7 Interrupt Enable Register 0 EINT0 100 8 4 8 Interrupt Enable Register 1 EINT1 101 8 4 9 Interrupt Operation Control Register INTCTL 102 8 4 10 EABASE 103 8 4 11 Interrupt Priority Register 0 INTPRI0 104 ...

Page 6: ...W DDR Slew 131 9 10 11 CLKOUT CLKOUT Divisor Output Control 132 9 10 12 DEVICE_ID Device ID 133 9 10 13 VDAC_CONFIG Video Dac Configuration 134 9 10 14 TIMER64_CTL Timer64 Input Control 135 9 10 15 USB_PHY_CTRL USB PHY Control 136 9 10 16 MISC Miscellaneous Control 138 9 10 17 MSTPRI0 Master Priorities 0 139 9 10 18 MSTPRI1 Master Priorities 1 140 9 10 19 VPSS_CLK_CTRL VPSS Clock Mux Control 141 9...

Page 7: ...Clock Management 172 12 3 1 Module Clock Disable 172 12 3 2 Module Clock Frequency Scaling 172 12 3 3 PLL Bypass and Power Down 172 12 4 ARM Sleep Mode Management 172 12 4 1 ARM Wait For Interrupt Sleep Mode 172 12 5 System Sleep Modes 173 12 5 1 Deep Sleep Mode 173 12 5 2 Fast NAND Boot Mode 173 12 6 I O Management 174 12 6 1 USB Phy Power Down 174 12 6 2 Video DAC Power Down 174 12 6 3 DDR Selft...

Page 8: ...tion Register PID 72 7 4 Interrupt Evaluation Register INTEVAL 73 7 5 Module Error Pending Register 0 mod 0 31 MERRPR0 74 7 6 Module Error Pending Register 1 mod 32 41 MERRPR1 75 7 7 Module Error Clear Register 0 mod 0 31 MERRCR0 76 7 8 Module Error Clear Register 1 mod 32 41 MERRCR1 77 7 9 Power Error Pending Register PERRPR 78 7 10 Power Error Clear Register PERRCR 79 7 11 External Power Control...

Page 9: ...LKOUT div out Control 132 9 11 DEVICE_ID Device ID 133 9 12 VDAC_CONFIG Video Dac Configuration 134 9 13 TIMER64_CTL Timer64 Input Control 135 9 14 USB_PHY_CTRL USB PHY Control 136 9 15 MISC Miscellaneous Control 138 9 16 MSTPRI0 Master Priorities 0 139 9 17 MSTPRI1 Master Priorities 1 140 9 18 VPSS_CLK_CTRL VPSS Clock Mux Control 141 9 19 DEEPSLEEP Deep Sleep Mode Configuration 142 9 20 DEBOUNCE ...

Page 10: ...ister CKSTAT Field Descriptions 60 6 20 SYSCLK Status Register SYSTAT Field Descriptions 61 6 21 PLL Controller Divider 4 Register PLLDIV4 Field Descriptions 62 7 1 Module Configuration 65 7 2 Module States 66 7 3 IcePick Emulation Commands 67 7 4 PSC Interrupt Events 68 7 5 PSC Registers 71 7 6 Peripheral Revision and Class Information Register PID Field Descriptions 72 7 7 Interrupt Evaluation R...

Page 11: ...rs 117 9 4 PINMUX0 Pin Mux 0 Video In Pin Mux Register Field Descriptions 118 9 5 PINMUX1 Pin Mux 1 Video Out Pin Mux Register Field Descriptions 120 9 6 PINMUX2 Pin Mux 2 AEMIF Pin Mux Register Field Descriptions 122 9 7 PINMUX3 Pin Mux 3 GIO Misc Pin Mux Register Field Descriptions 124 9 8 PINMUX4 Pin Mux 4 Misc Pin Mux Register Field Descriptions 127 9 9 BOOTCFG Boot Configuration Field Descrip...

Page 12: ...res and Special Modes 164 11 6 UART Data Sequences 169 11 7 Host Utility Data Format 170 11 8 CRC32 Table Transfer 170 12 1 Power Management Features 171 12 List of Tables SPRUFB3 September 2007 Submit Documentation Feedback ...

Page 13: ... to the functional specifications for the TMS320DM355 DMSoC SPRUFB3 TMS320DM355 ARM Subsystem Reference Guide This document describes the ARM Subsystem in the TMS320DM355 Digital Media System on Chip DMSoC The ARM subsystem is designed to give the ARM926EJ S ARM9 master control of the device In general the ARM is responsible for configuration and control of the device including the components of t...

Page 14: ...ommunication between the MMC SD controller and MMC SD card s is performed by the MMC SD protocol SPRUEE4 TMS320DM35x DMSoC Enhanced Direct Memory Access EDMA Controller Reference Guide This document describes the operation of the enhanced direct memory access EDMA3 controller in the TMS320DM35x Digital Media System on Chip DMSoC The EDMA controller s primary purpose is to service user programmed d...

Page 15: ...on Chip DMSoC SPRUFC8 TMS320DM355 DMSoC Peripherals Overview Reference Guide This document provides an overview of the peripherals in the TMS320DM355 Digital Media System on Chip DMSoC The following documents describe TMS320DM35x Digital Media System on Chip DMSoC that are not available by literature number Copies of these documents are available by title only on the internet at www ti com Contact...

Page 16: ...al external devices required for a complete digital camera digital implementation The interface is flexible enough to support various types of CCD and CMOS sensors signal conditioning circuits power management DDR2 mDDR SDRAM and shutter Iris and auto focus motor controls DM355 allows camera manufacturers to meet customer demands by fulfilling both image quality and low cost expectations required ...

Page 17: ...and SM Async One Nand EMIF2 3 USB 2 0 USB2 0 PHY Speaker microphone LD ASP 2x LD CM Buffer Logic VPSS MMC SD x2 SPI I F x3 UART x3 I2C Timer WDT x4 64 GIO PWM x4 RTO VPFE Enhanced channels 3PCC TC 100 MHz MPEG JPEG Coprocessor 1 3 ARM Subsystem in DM355 ARM Subsystem in DM355 The detailed DM355 block diagram is shown in Figure 1 1 Figure 1 1 DM355 Functional Block Diagram The ARM926EJ S 32 bit RIS...

Page 18: ...355 consists of the following components ARM926EJ S RISC processor including Coprocessor 15 CP15 MMU 16KB Instruction cache 8KB Data cache Write Buffer Java accelerator ARM Internal Memories 32KB Internal RAM 32 bit wide access 8KB Internal ROM ARM bootloader for non AEMIF boot options Embedded Trace Module and Embedded Trace Buffer ETM ETB System Control Peripherals ARM Interrupt Controller PLL C...

Page 19: ...D Video Processing Back End VPBE On Screen Display OSD Video Encoder Engine VENC Figure 2 1 shows the functional block diagram of the DM355 ARM Subsystem Figure 2 1 DM355 ARM Subsystem Block Diagram See the following related documents for more information DM355 Data Manual SPRS348 Provides a high level overview of the DM355 system DM355 Peripheral Reference Guides For various peripherals on the DM...

Page 20: ... off between high performance and high code density This includes features for efficient execution of Java byte codes and providing Java performance similar to Just in Time JIT Java interpreter without associated code overhead The ARM926EJ S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debugging The ARM926EJ S processor has a Harvard arch...

Page 21: ...fferent modes The stack pointer SP automatically changes to the SP of the mode that was entered Note See the ARM926EJ S TRM downloadable from http www arm com for more detailed information The processor status register PSR controls the enabling and disabling of interrupts and setting the mode of operation of the processor PSR 7 0 are the processor control bits PSR 27 8 are reserved bits and PSR 31...

Page 22: ...led information Table 3 1 Exception Vector Table for ARM Vector Offset Address Exception Mode on entry I Bit State on Entry F Bit State on Entry 0h Reset Supervisor Set Set 04h Undefined instruction Undefined Set Unchanged 08h Software interrupt Supervisor Set Unchanged 0Ch Pre fetch abort Abort Set Unchanged 10h Data abort Abort Set Unchanged 14h Reserved 18h IRQ IRQ Set Unchanged 1Ch FIQ FIQ Set...

Page 23: ...ing from 16 bit code to 32 bit code is folded into sub routine entry time Various portions of a system can be optimized for speed or for code density by switching between 16 BIS and 32 BIS execution as appropriate Note See the ARM926EJ S TRM downloadable from http www arm com for more detailed information The system control coprocessor CP15 is used to configure and control instruction and data cac...

Page 24: ...as follows Standard ARM architecture v4 and v5 MMU mapping sizes domains and access protection scheme Mapping sizes are 1 MB sections 64 KB large pages 4 KB small pages and 1 KB tiny pages Access permissions for large pages and small pages can be specified separately for each quarter of the page subpage permissions Hardware page table walks Invalidate entire TLB using CP15 register 8 Invalidate TL...

Page 25: ...ache write back operations removing the possibility of TLB misses related to the write back address Cache maintenance operations to provide efficient invalidation of the following The entire Dcache or Icache Regions of the Dcache or Icache The entire Dcache Regions of virtual memory They also provide operations for efficient cleaning and invalidation of the following The entire Dcache Regions of t...

Page 26: ...r 0 The instruction for reading the TCM status is given below MRC p15 0 Rd c0 c0 2 read TCM status register where Rd is any register where the status data is read into the register The format of the data in the TCM register is as shown below 31 17 16 SBZ UNP DTCM 15 1 0 SBZ UNP ITCM If the DTCM bit is 0 Data TCM is not present and if the DTCM bit is 1 Data TCM is present If the ITCM bit is 0 Instr...

Page 27: ...26ES J Subsystem in DM355 also includes the Embedded Trace Buffer ETB The ETM consists of two parts the trace port and triggering facilities The two ETM parts are shown in Table 3 5 Note The DM355 trace port is not pinned out Instead it is connected to a 4KB Embedded Trace Buffer ETB enabled debug tools are required to read interpret the captured trace data Table 3 5 ETM Part Descriptions ETM Part...

Page 28: ... narrow trace port An external Trace Port Analyzer TPA is used to capture the trace information Note See Chapter 10 of the Embedded Trace Macro cell Support of the ARM926EJ S TRM downloadable from http www arm com for more detailed information 28 ARM Core SPRUFB3 September 2007 Submit Documentation Feedback ...

Page 29: ...01 4000 0x0001 7FFF 16K ARM RAM1 Data ARM RAM1 ARM RAM1 0x0001 8000 0x0001 FFFF 32K ARM ROM Data ARM ROM ARM ROM only 8K used 0x0002 0000 0x000F FFFF 896K Reserved 0x0010 0000 0x01BB FFFF 26M 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Mem 0x01BC 1000 0x01BC 17FF 2K ARM ETB Reg Reserved 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved 0x01BC 1900 0x01BC FFFF 59136 Reserved 0x01BD 0000 0x01BF FFFF 192K 0...

Page 30: ...mory is with one wait state However if the ARM clock frequency is less than or equal to 150 MHz you may configure ARM access to internal memory to be zero wait state To configure the wait state use the bit AIM_WAIST in the Miscellaneous Control register MISC in the System Control Module MISC is described in Section 9 10 16 The ARM has access to the following external memories DDR2 mDDR Synchronous...

Page 31: ... EMIF AEMIF Controller Real Time Out RTO The ARM and EDMA also has access to the following internal peripherals ETM ETB ICEcrusher System Module PLL Controllers Power Sleep Controller ARM Interrupt Controller The ARM and EDMA also has access to the following internal peripherals Table 4 2 DM355 ARM Configuration Bus Access to Peripherals Address Accessibility Region Start End Size ARM EDMA EDMA CC...

Page 32: ... IF 0x01C7 0300 0x01C7 03FF 256 Video Encoder 0x01C7 0400 0x01C7 05FF 512 CCD Controller 0x01C7 0600 0x01C7 07FF 256 VPSS Buffer Logic 0x01C7 0800 0x01C7 08FF 256 CFA Multiply Mask Lens 0x01C7 0900 0x01C7 09FF 256 Distortion Image Pipe IPIPE 0x01C7 1000 0x01C7 3FFF 12K Reserved 0x01CC 0000 0x01CD FFFF 128K Reserved 0x01CD 0000 0x01CD 007F 128 Reserved 0x01CD 0380 0x01CD 03FF 128 Reserved 0x01CD F4...

Page 33: ...diate buffering for processing resizing of image data in the VPFE Numerous OSD display buffers Intermediate buffering for large raw Bayer data image files while performing still camera processing functions Buffering for intermediate data while performing video encode and decode functions Storage of executable firmware for the ARM etc DM355 s External Memory Interface EMIF provides an 8 bit or 16 b...

Page 34: ...emory cards ARM ROM supports booting of DM355 s ARM processor from NAND Flash located at CE0 The OneNAND mode supports the following features OneNAND Flash on up to two chip selects Supports only 16 bit data bus widths Supports asynchronous writes and reads Supports synchronous reads with continuous linear burst mode Does not support synchronous reads with wrap burst modes Programmable cycle timin...

Page 35: ... separeate PLL controllers PLLC1 and PLLC2 PLLC1 generates the clocks required by the ARM VPBE VPSS and peripherals PLL2 generates the clock required by the DDR PHY A block diagram of DM355 s clocking architecture is shown in Figure 5 1 The PLLs are described further in Chapter 6 Note Refer to the DM355 Data Manual SPRS348 for information on supported device clocking configurations e g supported P...

Page 36: ...SB 60 MHz Reference clock MXI MXO 24 MHz or 36 MHz Reference clock MXI MXO 24 MHz or 36 Mhz PCLK AUXCLK 1 BPDIV 3 SYSCLK1 CLKOUT3 SYSCLKBP CLKOUT2 EDMA Bus logic Sys logic PSC IcePick EXTCLK RTO USB Phy SYSCLKBP AUXCLK PLLDIV4 4 or 2 VPSS UART0 1 CLKOUT1 Sequencer SYSCLK4 5 2 Peripheral Clocking Considerations Peripheral Clocking Considerations Figure 5 1 DM355 Clocking Architecture Device Clockin...

Page 37: ...essing Back End VPBE Reference Guide for complete information on VPBE clocking The USB Controller is driven by two clocks an output clock of PLL1 and an output clock of the USB Phy The USB Phy clock is configurable by the USB Phy clock source bits PHYCLKSRC in the USB Phy control register USB_PHY_CTL in the System Control Module USBPHY_CTL is described in Chapter 9 When a 24 MHz crystal is used at...

Page 38: ... transitions on changing PLL settings Domain clocks alignment Clock gating PLL bypass PLL power down The various clock outputs given by the PLL controller are as follows Domain clocks SYSCLKn Bypass domain clock SYSCLKBP Auxiliary clock from reference clock AUXCLK Various dividers that can be used are as follows Pre PLL divider PREDIV Post PLL divider POSTDIV SYSCLK divider PLLDIV1 PLLDIVn SYSCLKB...

Page 39: ...le SYSCLK4 divider value is programmable program to 4 or 2 See the data manual for all supported configurations SYSCLKBP divider value is fixed to 3 SYSCLK1 is routed to the ARM Subsystem SYSCLK2 is routed to peripherals SYSCLK3 is routed to the VPBE module SYSCLK4 is routed to the VPSS module AUXCLK is routed to peripherals with fixed clock domain and also to the output pin CLKOUT1 SYSCLKBP is ro...

Page 40: ...be the customizations of PLLC2 in the DM355 Provides DDR PHY clock and CLKOUT3 Software configurable Accepts clock input or internal oscillator input same input as PLLC1 PLL pre divider value is programmable PLL multiplier value is programmable PLL post divider value is fixed to 1 Only SYSCLK 1 is used SYSCLK1 divider value is fixed to 1 SYSCLKBP divider value is fixed to 8 SYSCLK1 is routed to th...

Page 41: ...de is enabled and PLLM PREDIV POSTDIV and the PLL are used when PLLEN 0 bypass mode is enabled and PLLM PREDIV POSTDIV and the PLL are bypassed When bypass mode is enabled the input reference clock is directly input to the system clock dividers PLLDIVn The PLL controller defaults after reset to bypass mode When in PLL mode PLLEN 1 the input reference clock is supplied to divider PREDIV Divider PRE...

Page 42: ...ultiplier values 10 If necessary write PLLDIV to set PLLDIVn dividers Note that you must apply the GO operation to change these dividers to new ratios See Section 6 5 2 1 11 Wait at least 5 miro seconds for the PLL reset 12 In PLLCTL write PLLRST 0 de assert PLL reset 13 Wait at least 8000 reference clock cycles for the PLL to lock 14 In PLLCTL write PLLEN 1 to switch from bypass mode to PLL mode ...

Page 43: ...rted SYSCLKn toggles at the rate programmed in the RATIO field in PLLDIVn Any SYSCLKn with the corresponding ALNn bit in ALNCTL cleared to 0 remains free running during a GO operation SYSCLKn is not modified to the new RATIO rate in PLLDIVn SYSCLKn is not aligned to other SYSCLKs In DM355 do not program any ALNn bit in ALNCTL to 0 always program ALNCTL so that all SYSCLKs are aligned The GOSTAT bi...

Page 44: ... 1 In PLLCTL write PLLEN 0 bypass mode 2 Wait at least 4 reference clock cycles for the PLLEN mux to change 3 In PLLCTL write PLLPWRDN 1 to power down the PLL To wakeup the PLL from its power down mode follow the PLL sequence described in Section 6 5 1 1 Table 6 3 lists the base address for the PLLC1 and PLLC2 registers Table 6 4 lists the memory mapped registers for PLLC1 and PLLC2 Also see the d...

Page 45: ...Kn divider ratio change and align control register Section 6 6 13 144h DCHANGE PLL divider ratio change status register Section 6 6 14 148h CKEN Clock enable control AUXCLK Section 6 6 15 14Ch CKSTAT Clock status for SYSCLKBP and AUXCLK Section 6 6 16 150h SYSTAT Clock status for SYSCLKn clocks Section 6 6 17 160h PLLDIV4 Divider 4 control divider for SYSCLK4 Section 6 6 18 SPRUFB3 September 2007 ...

Page 46: ...t description figures throughout this section Figure 6 4 Peripheral ID Register PID 31 24 23 16 Reserved TYPE R 0 R 1 R 0 R 1 15 8 7 0 CLASS REV R 8 R 2 R 8 R 2 LEGEND R Read only n value after reset Table 6 5 Peripheral ID Register PID Field Descriptions Bit Field Value Description 31 24 Reserved Reserved 23 16 TYPE Peripheral Type 0x01 to identify as PLLC 15 8 CLASS Peripheral Class 0x08 7 0 REV...

Page 47: ... no effect for PLLC2 In DM355 a single oscillator or CLKIN square wave is input to both PLLC1 and PLLC2 0 Internal oscillator 1 CLKIN square wave 7 6 Reserved Reserved 5 PLLENSRC PLL enable source This bit must be cleared to 0 before PLLCTL PLLEN will have any effect 0 PLL enable is controlled by the register bit PLLCTL PLLEN 1 PLL enable is controlled by internal test hardware 4 PLLDIS PLL disabl...

Page 48: ...is 92 You may change the multiplier value from 92 to 184 Figure 6 6 PLL Multiplier Control Register PLLM 31 16 Reserved R 0 R 0 15 8 7 0 Reserved PLLM R 0 R W 179 R 0 R W 91 LEGEND R W Read Write R Read only n value after reset Table 6 7 PLL Multiplier Control Register PLLM Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 PLLM 5Bh PLL Multiplier Multiplier value PLLM 1 B...

Page 49: ...s Figure 6 7 PLL Pre Divider Control Register PREDIV 31 16 Reserved R 0 R 0 15 14 5 4 0 PREDEN Reserved RATIO R 1 R 0 R 7 R 1 R 0 R W 7 LEGEND R W Read Write R Read only n value after reset Table 6 8 PLL Pre Divider Control PREDIV Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 PREDEN Pre divider enable For PLLC1 and PLLC2 this bit must always be set to 1 0 Disable 1 Enab...

Page 50: ...it D1EN 1 Figure 6 8 PLL Controller Divider 1 Register PLLDIV1 31 16 Reserved R 0 R 0 15 14 5 4 0 D1EN Reserved RATIO R W 1 R 0 R 1 R W 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 6 9 PLL Controller Divider 1 Register PLLDIV1 Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 D1EN Divider enable for SYSCLK1 For PLLC1 this bit must always be set to 1...

Page 51: ... always be enabled bit D2EN 1 Figure 6 9 PLL Controller Divider 2 Register PLLDIV2 31 16 Reserved R 0 R 0 15 14 5 4 0 D2EN Reserved RATIO R W 1 R 0 R 3 R W 1 R 0 R 1 LEGEND R W Read Write R Read only n value after reset Table 6 10 PLL Controller Divider 2 Register PLLDIV2 Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 D2EN Divider enable for SYSCLK2 For PLLC1 and PLLC2 t...

Page 52: ...herefore all PLLDIV3 bit fields are reserved for PLLC2 Figure 6 10 PLL Controller Divider 3 Register PLLDIV3 31 16 Reserved R 0 R 0 15 14 5 4 0 D3EN Reserved RATIO R W 1 R 0 R W 9 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 6 11 PLL Controller Divider 3 Register PLLDIV3 Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 D3EN Divider enable for SYS...

Page 53: ...such that the post divider is equal to 1 But if DEV_SPEED is 1 or 3 it is not possible to change the post divider from the default value of 2 and thus the frequencies are limited The post divider for PLLC2 is always fixed cannot be changed to 1 Figure 6 11 PLL Post Divider Control Register POSTDIV 31 16 Reserved R 0 R 0 15 14 5 4 0 POSTDEN Reserved RATIO R 1 R 0 R 1 R 1 R 0 R 0 LEGEND R W Read Wri...

Page 54: ... divider must always be enabled bit BPDEN 1 Figure 6 12 Bypass Divider Register BPDIV 31 16 Reserved R 0 R 0 15 14 5 4 0 BPDEN Reserved RATIO R W 1 R 0 R 2 R W 1 R 0 R 7 LEGEND R W Read Write R Read only n value after reset Table 6 13 Bypass Divider Register BPDIV Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 BPDEN Divider enable for bypass clock This bit must always be...

Page 55: ...d only n value after reset Table 6 14 PLL Controller Command Register PLLCMD Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 GOSET GO operation command for SYSCLKn ratio change and or phase alignment Before setting this bit to 1 to initiate a GO operation check the GOSTAT bit in the PLLSTAT register to ensure all previous GO operations have completed 0 Clear bit Write of ...

Page 56: ... Register PLLSTAT 31 16 Reserved R 0 R 0 15 1 0 Reserved GOSTAT R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 6 15 PLL Controller Status PLLSTAT Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 GOSTAT GO status 0 GO operation is not in progress SYSCLK divider ratios and or phase alignment are not being changed 1 GO operation is in progress SYSCLK divider rat...

Page 57: ... Field Value Description 31 8 Reserved Reserved 7 0 ALNn SYSCLKn divider ratio change and alignment enable Do not change the default values of these fields ALN0 is divider ratio change and alignment enable for SYSCLK1 ALN1 is divider ratio change and alignment enable for SYSCLK2 ALN2 is divider ratio change and alignment enable for SYSCLK3 this bit is reserved for PLLC2 ALN3 is divider ratio chang...

Page 58: ... n value after reset Table 6 17 PLLDIV Ratio Change Status DCHANGE Field Descriptions Bit Field Value Description 31 8 Reserved Reserved 7 0 SYSn SYSCLKn divider ratio has been modified status When SYSn is 1 this bit indicates SYSCLKn ratio will be modified during GO operation SYS0 shows divider ratio has been modified for SYSCLK1 SYS1 shows divider ratio has been modified for SYSCLK2 SYS2 shows d...

Page 59: ...xiliary clock so the CKEN register is not applicable to PLLC2 and all CKEN bit fields are reserved for PLLC2 Figure 6 17 Clock Enable Control Register CKEN 31 16 Reserved R 0 R 0 15 1 0 Reserved AUXEN R 0 R W 1 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 6 18 Clock Enable Control Register CKEN Field Descriptions Bit Field Value Description 31 1 Reserved Reserved 0 AUXEN Aux...

Page 60: ...tus Register CKSTAT 31 16 Reserved R 0 R 0 15 4 3 2 1 0 Reserved BPON Reserved AUXEN R 0 R 1 R 0 R 1 R 0 R 1 R 0 R 0 LEGEND R Read only n value after reset Table 6 19 Clock Status Register CKSTAT Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 BPON SYSCLKBP status Shows the clock on off status for SYSCLKBP 0 Bypass clock is off 1 Bypass clock is on 2 1 Reserved 0 Reserved...

Page 61: ...lue after reset Table 6 20 SYSCLK Status Register SYSTAT Field Descriptions Bit Field Value Description 31 8 Reserved Reserved 7 0 SYSONn SYSCLKn status Shows the clock on off status for SYSCLKn SYSON0 shows clock on off status for SYSCLK1 SYSON1 shows clock on off status for SYSCLK2 SYSON2 shows clock on off status for SYSCLK3 this bit is reserved for PLLC2 SYSON3 shows clock on off status for SY...

Page 62: ...able to PLLC2 therefore all PLLDIV4 bit fields are reserved for PLLC2 Figure 6 20 PLL Controller Divider 4 Register PLLDIV4 31 16 Reserved R 0 R 0 15 14 5 4 0 D4EN Reserved RATIO R W 1 R 0 R W 3 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 6 21 PLL Controller Divider 4 Register PLLDIV4 Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 D4EN Divider...

Page 63: ...k ON OFF Control module resets Supports IcePick emulation features power clock and reset Figure 7 1 DM355 Power and Sleep Controller PSC The DM355 system includes one power domain and forty one separate modules as shown in Figure 7 2 and summarized in Table 7 1 The DM355 s power domain is always on when the chip is on and it is referred to as the AlwaysOn power domain The AlwaysOn domain is powere...

Page 64: ...SS CLKDIV 2 domain PLL1 Always on power domain CLDIV 4 domain IcePick AEMIF HPI USB ASP1 ASP0 MMC1 MMC0 Mem Stick EDMA SPI1 PSC GPIO Power PWM 2 PWM 3 MPEG JPEG Coprocessor MJCP DM355 Power Domain and Module Topolgy Figure 7 2 DM355 Power Domain and Module Topology Power and Sleep Controller 64 SPRUFB3 September 2007 Submit Documentation Feedback ...

Page 65: ... 0 01 Enable OneNAND BTSEL 1 0 10 SyncRst MMC SD BTSEL 1 0 11 Enable UART 15 MMC SD0 AlwaysOn ON BTSEL 1 0 00 SyncRst NAND BTSEL 1 0 01 SyncRst OneNAND BTSEL 1 0 10 Enable MMC SD BTSEL 1 0 11 SyncRst UART 16 MemStick AlwaysOn ON SyncRst 17 ASP0 AlwaysOn ON SyncRst 18 I2C AlwaysOn ON SyncRst 19 UART0 AlwaysOn ON BTSEL 1 0 00 SyncRst NAND BTSEL 1 0 01 SyncRst OneNAND BTSEL 1 0 10 SyncRst MMC SD BTSE...

Page 66: ...ower to the power domain is on OFF power to the power domain is off In DM355 the AlwaysOn Power Domain is always in the ON state when the chip is powered on A module can be in one of four states Disable Enable SwRstDisable or SyncReset These four states correspond to combinations of module reset asserted or de asserted and module clock on or off as shown in Table 7 2 Note Reset of a module is defi...

Page 67: ...matically transitioned to the ON state upon power on reset No software intervention is required the transition is automatically handled by the hardware This section describes the procedure for transitioning the module state The procedure for module state transitions is as follows x corresponds to the module Wait for the GOSTATx bit in PTSTAT to clear to 0x0 You must wait for any previously initiat...

Page 68: ...t is named PSCINT in the ARM interrupt map The PSC interrupt is generated when certain IcePick emulation events occur The PSC interrupt is generated when any of the following events occur Power Domain Emulation Event Module State Emulation Event Module Local Reset Emulation Event External Power Control Pending Event These interrupt events are summarized in Table 7 4 and described in more detail in...

Page 69: ...o or removed from the power pins See Section 7 4 1 for more information The PSC interrupt enable bits are the EMUIHB bit in PDCTLx the EMUIHB bit in MDCTL x the EMURSTIE bit in MDCTL x and the EPx bit in EPCPR Note To interrupt the ARM the ARM s power and sleep controller interrupt PSCINT must also be enabled in the ARM interrupt controller See Chapter 8 for more information on the ARM s power and...

Page 70: ...vent so effectively this event is always enabled The PSC interrupt is sent to the ARM interrupt controller when at least one enabled event becomes active 2 Enable the ARM s power and sleep controller interrupt PSCINT in the ARM interrupt controller To interrupt the ARM PSCINT must be enabled in the ARM interrupt controller See Chapter 8 for more information 70 Power and Sleep Controller SPRUFB3 Se...

Page 71: ...n particular registers associated with module 39 are reserved and must not be read or written Table 7 5 PSC Registers Offset Register Description Section 0h PID Peripheral Revision and Class Information Section 7 7 1 18h INTEVAL Interrupt Evaluation Register Section 7 7 2 40h MERRPR0 Module Error Pending Register 0 Section 7 7 3 44h MERRPR1 Module Error Pending Register 1 Section 7 7 4 50h MERRCR0...

Page 72: ... 0 RTL MAJOR CUSTOM MINOR R 0 R 1 R 0 R 5 LEGEND R Read only n value after reset Table 7 6 Peripheral Revision and Class Information Register PID Field Descriptions Bit Field Value Description 31 30 SCHEME 0 3h Scheme 29 28 Reserved 0 Reserved 27 16 FUNC 0 FFFh Software compatible 15 11 RTL 0 1Fh RTL Version 10 8 MAJOR 0 7h Major Revision 7 6 CUSTOM 0 3h Indicates a special version for a particula...

Page 73: ...ved R 0 15 1 0 Reserved Reserved ALLEV R 0 R W 0 LEGEND R Read only n value after reset Table 7 7 Interrupt Evaluation Register INTEVAL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 Reserved Reserved 0 ALLEV Re evaluate PSC interrupt 0 A write of 0 has no effect 1 Write 1 to re evaluate the interrupt condition SPRUFB3 September 2007 Power and Sleep Controller 73 Submit ...

Page 74: ...ing Register 0 mod 0 31 MERRPR0 31 0 M0 32 R 0 LEGEND R Read only n value after reset Table 7 8 Module Error Pending Register 0 mod 0 31 MERRPR0 Field Descriptions Bit Field Value Description 31 0 M0 32 Module interrupt status bit for modules 0 31 0 Power domain interrupt is not active 1 Power domain interrupt is active 74 Power and Sleep Controller SPRUFB3 September 2007 Submit Documentation Feed...

Page 75: ... MERRPR1 31 16 Reserved R 0 15 9 8 0 Reserved M 9 R 0 R 0 LEGEND R Read only n value after reset Table 7 9 Module Error Pending Register 1 mod 32 41 MERRPR1 Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 0 M 9 Module interrupt status bit for modules 32 41 0 Power domain interrupt is not active 1 Power domain interrupt is active SPRUFB3 September 2007 Power and Sleep Cont...

Page 76: ... M 32 R 0 LEGEND R Read only n value after reset Table 7 10 Module Error Clear Register 0 mod 0 31 MERRCR0 Field Descriptions Bit Field Value Description 31 0 M 32 Clears the interrupt bit set in the corresponding MERRPRO register bit field and the MDSTAT interrupt bit fields This pertains to modules 0 31 0 A write of 0 has no effect 1 Clears module interrupt 76 Power and Sleep Controller SPRUFB3 ...

Page 77: ... R 0 W 0 LEGEND R W Read Write R Read only n value after reset Table 7 11 Module Error Clear Register 1 mod 32 41 MERRCR1 Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 0 M 9 Clears the interrupt bit set in the corresponding MERRPR1 register bit field and the MDSTAT interrupt bit fields This pertains to modules 32 41 0 A write of 0 has no effect 1 Clears module interrupt...

Page 78: ...PR 31 16 Reserved R 0 15 2 1 0 Reserved P 1 R 0 R 0 LEGEND R Read only n value after reset Table 7 12 Power Error Pending Register PERRPR Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 P 1 Power domain interrupt status 0 Power domain interrupt is not active 1 Power domain interrupt is active 78 Power and Sleep Controller SPRUFB3 September 2007 Submit Documentation Feed...

Page 79: ...16 Reserved R 0 15 2 1 0 Reserved P 1 R 0 W 0 LEGEND R W Read Write R Read only n value after reset Table 7 13 Power Error Clear Register PERRCR Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 P 1 Clears the power domain interrupt 0 A write of 0 has no effect 1 Clears the power domain interrupt SPRUFB3 September 2007 Power and Sleep Controller 79 Submit Documentation Fe...

Page 80: ...ly n value after reset Table 7 14 External Power Control Pending Register EPCPR Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 EPC 1 External power control pending bit The PSC sets this bit indicating it is ready for an external controller to apply power to the external power pins of the power domain 0 The PSC is not requesting external power control 1 The PSC requests...

Page 81: ...er EPCCR 31 16 Reserved R 0 15 2 1 0 Reserved EPC 1 R 0 W 0 LEGEND R Read only n value after reset Table 7 15 External Power Control Clear Register EPCCR Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 EPC 2 External power control clear bit 0 A write of 0 has no effect 1 Set this bit to clear the EPCPR interrupt SPRUFB3 September 2007 Power and Sleep Controller 81 Submi...

Page 82: ...D R W Read Write R Read only n value after reset Table 7 16 Power Domain Transition Command Register PTCMD Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 GO 1 Power domain GO transition command 0 A write of 0 has no effect 1 Writing 1 causes the state transition interrupt generation block to evaluate the new PTNEXT and the NEXT states in MDCTL as the desired states of th...

Page 83: ...OSTAT 1 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 7 17 Power Domain Transition Status Register PTSTAT Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 GOSTAT 1 Power domain transition status 0 No transition in progress 1 Power domain is transitioning i e either the power domain is transitioning or modules in this power domain are transitioning SPR...

Page 84: ...tion 31 12 Reserved 0 Reserved 11 EMUIHB Emulation alters domain state 0 Interrupt is not active 1 Interrupt is active 10 Reserved Reserved 9 PORDONE Power_On_Reset POR Done status 0 Power domain POR is not done 1 Power domain POR is done 8 POR Power Domain Power_On_Reset POR status This bit reflects the POR status for this power domain including all modules in the domain 0 Power domain POR is ass...

Page 85: ... 10 9 8 7 1 0 Reserved EMUIHBIE EPCGOOD Reserved NEXT R 0 R W 0 R W 0 R 0 R W 0 LEGEND R Read only n value after reset Table 7 19 Power Domain Control n Register PDCTLn Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 EMUIHBIE Emulation alters power domain state interrupt enable 0 Disable interrupt 1 Enable interrupt 8 EPCGOOD External power control power good indication ...

Page 86: ...errupt active 16 EMURST Emulation alters module reset interrupt active 0 Interrupt not active 1 Interrupt active 15 13 Reserved 0 Reserved 12 MCKOUT Module clock output status Shows status of module clock ON OFF 0 Module clock is off 1 Module clock is on 11 MRSTDONE Module reset done Software is responsible for checking that mode reset is done before accessing the module 0 Module reset is not done...

Page 87: ...40 and 41 Figure 7 18 Module Control n Register 0 41 MDCTLn 31 16 Reserved R 0 15 11 10 9 8 4 0 Reserved EMUIHBIE EMURSTIE Reserved NEXT R 0 R W 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 21 Module Control n Register 0 41 MDCTLn Field Descriptions Bit Field Value Description 31 11 Reserved 0 Reserved 10 EMUIHBIE Interrupt enable for emulation alters module stat...

Page 88: ...Q interrupt routine can read the ENTRY register and jump to the corresponding ISR directly Thus the ARM does not require a software dispatcher to determine the asserted interrupt The AINTC takes up to 64 ARM device interrupts and maps them to either the IRQ or to the FIQ of the ARM Each interrupt is also assigned one of 8 priority levels 2 for FIQ 6 for IRQ For interrupts with the same priority le...

Page 89: ...PINT2 1 SPI2 53 GPIO9 GPIO 22 TINT7 Timer3 TINT34 54 GPIOBNK0 GPIO 23 SDIOINT0 SDIO0 55 GPIOBNK1 GPIO 24 MBXINT0 or ASP0 or 56 GPIOBNK2 GPIO MBXINT1 ASP1 25 MBRINT0 or ASP0 or 57 GPIOBNK3 GPIO MBRINT1 ASP1 26 MMCINT0 MMC SD0 58 GPIOBNK4 GPIO 27 MMCINT1 MMC SD1 59 GPIOBNK5 GPIO 28 PWMINT3 PWM3 60 GPIOBNK6 GPIO 29 DDRINT DDR EMIF 61 COMMTX ARMSS 30 AEMIFINT Async EMIF 62 COMMRX ARMSS 31 SDIOINT1 SDI...

Page 90: ...iate IRQ FIQ registers capture interrupt events Each event causes an IRQ or FIQ to generate only if the corresponding EINT bit enables it The EINT bit enables or disables the event regardless of whether it is mapped to IRQ or to FIQ The IRQ FIQ register always captures each event regardless of whether the interrupt is actually enabled Event priority is determined using both a fixed and a programma...

Page 91: ...e ARM reads the register They may also change immediately after a read by the ARM if a higher priority event occurs If no IRQ mapped effective interrupt is pending then the IRQENTRY value reflects the EABASE value Similarly if no FIQ mapped effective interrupt is pending then the FIQENTRY value reflects the EABASE value 1 For the FIQENTRY If FERAW is 0 FIQENTRY reflects the state of the highest pr...

Page 92: ...r interrupts are pending then the IRQz FIQz output to the ARM may also go inactive Enabling the interrupt if it is already pending takes immediate affect This is shown in Figure 8 3 Figure 8 3 Immediate Interrupt Disable Enable If IDMODE is 1 then the EINT effect is delayed Essentially the active interrupt status is latched until cleared by the ARM If EINT is cleared the prioritizer continues to u...

Page 93: ... Entry Address 28 0 for valid IRQ interrupt Section 8 4 6 18h EINT0 Interrupt Enable Register 0 Section 8 4 7 1Ch EINT1 Interrupt Enable Register 1 Section 8 4 8 20h INTCTL Interrupt Operation Control Register Section 8 4 9 24h EABASE Interrupt Entry Table Base Address Section 8 4 10 30h INTPRI0 Interrupt 0 7 Priority select Section 8 4 11 34h INTPRI1 Interrupt 8 15 Priority select Section 8 4 12 ...

Page 94: ...atus of INT 31 0 if mapped to FIQ 31 16 FIQ 31 0 R W 1 15 0 FIQ 31 0 R W 1 LEGEND R W Read Write n value after reset Table 8 3 Interrupt Status of INT 31 0 if mapped to FIQ Field Descriptions Bit Field Value Description 31 0 FIQ 31 0 Interrupt status of INTx if mapped to FIQ 0 Rd Interrupt occurred 1 Wr Acknowledge interrupt 94 Interrupt Controller SPRUFB3 September 2007 Submit Documentation Feedb...

Page 95: ...INT 63 32 if mapped to FIQ 31 16 FIQ 63 32 R 1 15 0 FIQ 63 31 R W 1 LEGEND R W Read Write R Read only n value after reset Table 8 4 Interrupt Status of INT 63 32 if mapped to FIQ Field Descriptions Bit Field Value Description 31 0 FIQ 63 32 Interrupt status of INTx if mapped to FIQ 0 Rd Interrupt occurred 1 Wr Acknowledge interrupt SPRUFB3 September 2007 Interrupt Controller 95 Submit Documentatio...

Page 96: ... 31 0 if mapped to IRQ 31 16 IRQ 31 0 R W 1 15 0 IRQ 31 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 8 5 Interrupt Status of INT 31 0 if mapped to IRQ Field Descriptions Bit Field Value Description 31 1 IRQ 31 0 Interrupt status of INTx if mapped to IRQ 0 Rd Interrupt occurred 1 Wr Acknowledge interrupt 96 Interrupt Controller SPRUFB3 September 2007 Submit Documentation Feed...

Page 97: ...T 31 0 if mapped to IRQ 31 16 IRQ 63 32 R W 1 15 0 IRQ 63 32 R W 1 LEGEND R W Read Write R Read only n value after reset Table 8 6 Interrupt Status of INT 31 0 if mapped to IRQ Field Descriptions Bit Field Value Description 31 0 IRQ Interrupt status of INTx if mapped to IRQ 0 Rd Interrupt occurred 1 Wr Acknowledge interrupt SPRUFB3 September 2007 Interrupt Controller 97 Submit Documentation Feedba...

Page 98: ... 8 9 Fast Interrupt Request Entry Address Register FIQENTRY 31 16 FIQENTRY R 0 15 0 FIQENTRY R 0 LEGEND R Read only n value after reset Table 8 7 Fast Interrupt Request Entry Address Register FIQENTRY Field Descriptions Bit Field Value Description 31 0 FIQENTRY Interrupt entry table address of the current highest priority FIQ 98 Interrupt Controller SPRUFB3 September 2007 Submit Documentation Feed...

Page 99: ... 8 10 Interrupt Request Entry Address Register IRQENTRY 31 16 IRQENTRY R 0 15 0 IRQENTRY R 0 LEGEND R Read only n value after reset Table 8 8 Interrupt Request Entry Address Register IRQENTRY Field Descriptions Bit Field Value Description 31 0 IRQENTRY Interrupt entry table address of the current highest priority IRQ SPRUFB3 September 2007 Interrupt Controller 99 Submit Documentation Feedback ...

Page 100: ...rrupt Enable Register 0 EINT0 31 16 EINT 31 0 R W 0 15 0 EINT 31 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 8 9 Interrupt Enable Register 0 EINT0 Field Descriptions Bit Field Value Description 31 0 EINT 31 0 Interrupt enable for INTx 0 Mask interrupt 1 Enable interrupt 100 Interrupt Controller SPRUFB3 September 2007 Submit Documentation Feedback ...

Page 101: ...nterrupt Enable Register 1 EINT1 31 16 EINT 63 32 R 0 15 0 EINT 63 32 R W 0 LEGEND R W Read Write R Read only n value after reset Table 8 10 Interrupt Enable Register 1 EINT1 Field Descriptions Bit Field Value Description 31 0 EINT Interrupt enable for INTx 0 Mask interrup 1 Enable interrupt SPRUFB3 September 2007 Interrupt Controller 101 Submit Documentation Feedback ...

Page 102: ...EGEND R W Read Write R Read only n value after reset Table 8 11 Interrupt Operation Control Register INTCTL Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 IDMODE Interrupt disable mode 0 Disable immediately 1 Disable after ack 1 IERAW Masked interrupt reflected in the IRQENTRY register 0 Disable reflect 1 Enable reflect 0 FERAW Masked interrupt reflect in FIQENTRY regist...

Page 103: ... R W 0 LEGEND R W Read Write R Read only n value after reset Table 8 12 EABASE Field Descriptions Bit Field Value Description 31 29 Reserved Reserved 28 3 EABASE Interrupt entry table base address 8 byte aligned 2 Reserved Reserved 1 0 SIZE Size of each entry in the interrupt entry table 0 4 bytes 1h 8 bytes 2h 16 bytes 3h 32 bytes SPRUFB3 September 2007 Interrupt Controller 103 Submit Documentati...

Page 104: ...ad Write R Read only n value after reset Table 8 13 Interrupt Priority Register 0 INTPRI0 Field Descriptions Bit Field Value Description 31 Reserved Reserved 30 28 INT7 Selects INT7 priority level 27 Reserved Reserved 26 24 INT6 Selects INT6 priority level 23 Reserved Reserved 22 20 INT5 Selects INT5 priority level 19 Reserved Reserved 18 16 INT4 Selects INT4 priority level 15 Reserved Reserved 14...

Page 105: ...Write R Read only n value after reset Table 8 14 Interrupt Priority Register 1 INTPRI1 Field Descriptions Bit Field Value Description 31 Reserved Reserved 30 28 INT15 Selects INT15 priority level 27 Reserved Reserved 26 24 INT14 Selects INT14 priority level 23 Reserved Reserved 22 20 INT13 Selects INT13 priority level 19 Reserved Reserved 18 16 INT12 Selects INT12 priority level 15 Reserved Reserv...

Page 106: ...rite R Read only n value after reset Table 8 15 Interrupt Priority Register 2 INTPRI2 Field Descriptions Bit Field Value Description 31 Reserved Reserved 30 28 INT23 Selects INT23 priority level 27 Reserved Reserved 26 24 INT22 Selects INT22 priority level 23 Reserved Reserved 22 20 INT21 Selects INT21 priority level 19 Reserved Reserved 18 16 INT20 Selects INT20 priority level 15 Reserved Reserve...

Page 107: ...rite R Read only n value after reset Table 8 16 Interrupt Priority Register 3 INTPRI3 Field Descriptions Bit Field Value Description 31 Reserved Reserved 30 28 INT31 Selects INT31 priority level 27 Reserved Reserved 26 24 INT30 Selects INT30 priority level 23 Reserved Reserved 22 20 INT29 Selects INT29 priority level 19 Reserved Reserved 18 16 INT28 Selects INT28 priority level 15 Reserved Reserve...

Page 108: ...rite R Read only n value after reset Table 8 17 Interrupt Priority Register 4 INTPRI4 Field Descriptions Bit Field Value Description 31 Reserved Reserved 30 28 INT39 Selects INT39 priority level 27 Reserved Reserved 26 24 INT38 Selects INT38 priority level 23 Reserved Reserved 22 20 INT37 Selects INT37 priority level 19 Reserved Reserved 18 16 INT36 Selects INT36 priority level 15 Reserved Reserve...

Page 109: ...rite R Read only n value after reset Table 8 18 Interrupt Priority Register 5 INTPRI5 Field Descriptions Bit Field Value Description 31 Reserved Reserved 30 28 INT47 Selects INT47 priority level 27 Reserved Reserved 26 24 INT46 Selects INT46 priority level 23 Reserved Reserved 22 20 INT45 Selects INT45 priority level 19 Reserved Reserved 18 16 INT44 Selects INT44 priority level 15 Reserved Reserve...

Page 110: ...rite R Read only n value after reset Table 8 19 Interrupt Priority Register 6 INTPRI6 Field Descriptions Bit Field Value Description 31 Reserved Reserved 30 28 INT55 Selects INT55 priority level 27 Reserved Reserved 26 24 INT54 Selects INT54 priority level 23 Reserved Reserved 22 20 INT53 Selects INT53 priority level 19 Reserved Reserved 18 16 INT52 Selects INT52 priority level 15 Reserved Reserve...

Page 111: ...rite R Read only n value after reset Table 8 20 Interrupt Priority Register 7 INTPRI7 Field Descriptions Bit Field Value Description 31 Reserved Reserved 30 28 INT63 Selects INT63 priority level 27 Reserved Reserved 26 24 INT62 Selects INT62 priority level 23 Reserved Reserved 22 20 INT61 Selects INT61 priority level 19 Reserved Reserved 18 16 INT60 Selects INT60 priority level 15 Reserved Reserve...

Page 112: ...er Managment Deep Sleep Control Bandwidth Management Bus master DMA priority control This chapter describes the system control module The DEVICE_ID register of the System Control Module contains a software readable version of the JTAG ID device Software can use this register to determine the version of the device on which it is executing The register format and description are shown in Table 9 11 ...

Page 113: ...2 with descriptions in Table 9 5 The PINMUX2 register controls pin multiplexing for the AEMIF pins The register format is shown in Figure 9 3 A brief description of each field is shown in Table 9 6 The PINMUX3 register controls pin multiplexing for the GIO pins The register format is shown in Figure 9 4 A brief description of each field is shown in Table 9 7 The PINMUX4 register controls pin multi...

Page 114: ...t pins CLKOUT 3 1 The purpose of these pins is to provide input clock to external components which are CCD clock to the AFE TG audio clock and clock for motor control The CCD clock is the input crystal clock fed undivided directly to the pin CLKOUT1 the audio clock is a divide by 3 clock CLKOUT2 and the motor control is a divide by 8 clock CLKOUT3 The register CLKOUT is the CLK_OUT 3 1 divsor and ...

Page 115: ... DM355 master is shown in Table 9 1 Table 9 1 DM355 Master IDs MSTID Master 0 ARM Instruction 1 ARM Data 2 Reserved 3 Reserved 4 7 Reserved 8 VPSS 9 MPEG JPEG Coprocessor MJCP 10 EDMA 11 15 Reserved 16 EDMA Channel 0 read 17 EDMA Channel 0 write 18 EDMA Channel 1 read 19 EDMA Channel 1 write 20 31 Reserved 32 Reserved 33 Reserved 34 USB 35 Reserved 36 Reserved 37 Reserved 38 63 Reserved SPRUFB3 Se...

Page 116: ...I registers The default priority level for each DM355 bus master is shown in Table 9 2 Application software is expected to modify these values to obtain the desired system performance Table 9 2 DM355 Default Master Priorities Master Default Priority VPSS 0 1 EDMA Ch 0 0 2 EDMA Ch 1 0 2 ARM DMA 1 ARM CFG 1 Reserved Reserved Reserved Reserved USB 4 Reserved Reserved Reserved MPEG JPEG Coprocessor MJ...

Page 117: ...ut Control Section 9 10 11 28h DEVICE_ID Device ID Section 9 10 12 2Ch VDAC_CONFIG Video DAC Configuration Section 9 10 13 30h TIMER64_CTL TIMER64_CTL Timer64 Input Control Section 9 10 14 34h USB_PHY_CTRL USB PHY Control Section 9 10 15 38h MISC Miscellaneous Control Section 9 10 16 3Ch MSTPRI0 Master Priorities Reg0 Section 9 10 17 40h MSTPRI1 Master Priorities Reg1 Section 9 10 18 44h VPSS_CLK_...

Page 118: ...Value Description 31 15 RESERVED Reserved Must be set to 0 14 PCLK Enable the PCLK Video In Pin Mux 0 GIO 82 1 PCLK 13 CAM_WEN Enable the CAM_WEN Video In Pin Mux 0 GIO 83 1 CAM_WEN 12 CAM_VD Enable the CAM_VD Video In Pin Mux 0 GIO 84 1 CAM_VD 11 CAM_HD Enable the CAM_HD Video In Pin Mux 0 GIO 85 1 CAM_HD 10 YIN_70 Enable the YIN 7 0 Video In Pin Mux 0 GIO 93 86 1 YIN 7 0 9 CIN_10 Enable the CIN ...

Page 119: ... Field Descriptions continued Bit Field Value Description 3 2 CIN_6 Enable the CIN 6 Video In Pin Mux 0 GIO 100 1 CIN 6 2 SPI 2 _SDO 3 _RESV 1 0 CIN_7 Enable the CIN 7 Video In Pin Mux 0 GIO 101 1 CIN 7 2 SPI 2 _SCLK 3 _RESV SPRUFB3 September 2007 System Control Module 119 Submit Documentation Feedback ...

Page 120: ... Register Field Descriptions Bit Field Value Description 31 23 RESERVED Reserved Must be set to 0 22 VCLK Enable VCLK Video Out Pin Mux 0 VCLK 1 GIO 68 21 20 EXTCLK Enable EXTCLK Video Out Pin Mux 0 GIO 69 1 EXTCLK 2 R2 3 PWM3 19 18 FIELD Enable FIELD Video Out Pin Mux 0 GIO 70 1 FIELD 2 B2 3 PWM3 17 DLCD Enable DLCD Signal Video Out Pin Mux 0 LCD_OE or BRIGHT 1 GIO 71 16 HVSYNC Enable HVSYNC Vide...

Page 121: ...IO 77 1 COUT 3 2 PWM2 3 RTO2 7 6 COUT_4 Enable COUT 4 Video Out Pin Mux 0 GIO 78 1 COUT 4 2 PWM2 3 RTO1 5 4 COUT_5 Enable COUT 5 Video Out Pin Mux 0 GIO 79 1 COUT 5 2 PWM2 3 RTO0 3 2 COUT_6 Enable COUT 6 Video Out Pin Mux 0 GIO 80 1 COUT 6 2 PWM1 3 RSVD 1 0 COUT_7 Enable COUT 7 Video Out Pin Mux 0 GIO 81 1 COUT 7 2 PWM0 3 RSVD SPRUFB3 September 2007 System Control Module 121 Submit Documentation F...

Page 122: ...lue Description 31 12 RESERVED Reserved Must be set to 0 11 EM_CLK Enable EM_CLK AEMIF Pin Mux 0 EM_CLK 1 GIO 31 10 EM_AVD Enable EM_AVD AEMIF Pin Mux 0 EM_AVD Address Valid Detect for OneNAND 1 GIO 32 9 EM_WAIT Enable EM_WAIT AEMIF Pin Mux 0 EM_WAIT 1 GIO 33 8 EM_WE_OE Enable EM_WE_OE AEMIF Pin Mux 0 EM_WE EM_OE 1 GIO 35 34 7 EM_CE1 Enable EM_CE1 AEMIF Pin Mux 0 EM_A0 1 GIO 36 6 EM_CE0 Enable EM_...

Page 123: ... for OneNAND 0 EM_BA0 Byte address for 8 bit data bus 1 EM_A14 Address MSB required for OneNAND 2 GIO 54 3 RSVD 1 EM_A0_BA1 Enable EM_A0 BA1 AEMIF Pin Mux Reset value set by AECFG 0 sets AEMIF address width for boot OneNAND operation requires PINMUX2 4 1 AECFG 3 0 0010b i e 16_bit data bus full AEMIF address bus plus EM_A 14 EM_BA1 used as 16_bit address This puts the AEMIF module in Half Rate mod...

Page 124: ... n value after reset Table 9 7 PINMUX3 Pin Mux 3 GIO Misc Pin Mux Register Field Descriptions Bit Field Value Description 31 29 RESERVED Reserved Must be set to 0 28 GIO7 Enable GIO 7 GPIO Pin Mux 0 GIO 7 1 SPI0_SDENA 1 27 GIO8 Enable GIO 8 GPIO Pin Mux 0 GIO 8 1 SPI1_SDO 26 25 GIO9 Enable GIO 9 GPIO Pin Mux 0 GIO 9 1 SPI1_SDI 2 SPI1_SDENA 1 3 24 GIO10 Enable GIO 10 GPIO Pin Mux 0 GIO 10 1 SPI1_SC...

Page 125: ...3 RSVD 11 10 GIO21 Enable GIO 21 GPIO Pin Mux 0 GIO 21 1 SD1_DATA2 2 UART2_CTS 3 RSVD 9 8 GIO22 Enable GIO 22 GPIO Pin Mux 0 GIO 22 1 SD1_DATA3 2 UART2_RTS 3 RSVD 7 GIO23 Enable GIO 23 GPIO Pin Mux 0 GIO 23 1 SD1_CMD 6 GIO24 Enable GIO 24 GPIO Pin Mux 0 GIO 24 1 SD1_CLK 5 GIO25 Enable GIO 25 GPIO Pin Mux 0 GIO 25 1 ASP0_BFSR 4 GIO26 Enable GIO 26 GPIO Pin Mux 0 GIO 26 1 ASP0_R 3 GIO27 Enable GIO 2...

Page 126: ...ns Table 9 7 PINMUX3 Pin Mux 3 GIO Misc Pin Mux Register Field Descriptions continued Bit Field Value Description 0 GIO30 Enable GIO 30 GPIO Pin Mux 0 GIO 30 1 ASP0_BDX 126 System Control Module SPRUFB3 September 2007 Submit Documentation Feedback ...

Page 127: ...ENA R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 9 8 PINMUX4 Pin Mux 4 Misc Pin Mux Register Field Descriptions Bit Field Value Description 31 3 RESERVED Reserved Must be set to 0 2 MMCSD0_MS Enable MMCSD0_MS 0 MMC SD 0 SD0_CLK SD0_CMD SD0_DATA 3 0 1 MS MSCLK MS_BS MS_DATA 3 0 1 SPIO_SDI Enable SPI0_SDI 0 SPI0_SDI 1 GIO 32 0 SPI0_SDENA Enable SPI0_SDENA0 0 SPI0...

Page 128: ... 0 are compatible with the boot mode OneNAND boot requires AECFG 3 0 0010b Only 8_bit NAND boot is supported AECFG 3 0 1XXXb 0 Boot from ROM NAND Flash boot mode 1 Boot from AEMIF OneNAND 2 Boot from ROM SD0 boot mode 3 Boot from ROM UART0 boot mode 5 4 RESERVED Reserved 3 0 AECFG AEMIF Configuration settings for boot by AECFG 3 0 pins 3 AEMIF Data Bus width 0 16 bit 1 8 bit 2 1 Configuration of E...

Page 129: ...RM Interrupt Mux Control Register Field Descriptions Bit Field Value Description 31 8 RESERVED Reserved 7 INT20 INT20 PSC or Reserved 0 Power Sleep Controller 1 Reserved 6 INT25 INT25 ASP0 RINT or ASP1 RINT 0 ASP0 RINT 1 ASP1 RINT 5 INT24 INT24 ASP0 XINT or ASP1 XINT 0 ASP0 XINT 1 ASP1 XINT 4 INT19 INT19 SPI2_INT0 or EDMA TC1 Error Interrupt 0 SPINT2_0 1 EDMA TC1 Error 3 INT18 INT18 SPI1_INT1 or E...

Page 130: ...ED EVT26 EVT9 EVT8 R 0 R W 0 R W 0 R W 0 LEGEND R Read only n value after reset Table 9 11 EDMA_EVTMUX EDMA Event Mux Control Register Field Descriptions Bit Field Value Description 31 3 RESERVED Reserved 2 EVT26 EVT26 MMC SD 0 Receive or MS 0 MMC SD 0 Receive Event 1 MS Event 1 EVT9 EVT9 ASP1 Receive or Timer2 TINT5 0 ASP1 Receive Event 1 TIMER2 TINT5 0 EVT8 EVT9 ASP1 transmit or Timer2 TINT4 0 A...

Page 131: ... R 0 15 4 3 2 1 0 RESERVED DDRDATA_ DDRCMD_ SLEW SLEW R 0 R 0 R 0 LEGEND R Read only n value after reset Table 9 12 DDR_SLEW DDR Slew Field Descriptions Bit Field Value Description 31 4 RESERVED Reserved 3 2 DDRDATA_SLEW DDR data slew programmed in eFuse 1 0 DDRCMD_SLEW DDR command slew programmed in eFuse SPRUFB3 September 2007 System Control Module 131 Submit Documentation Feedback ...

Page 132: ...gure 9 10 CLKOUT CLKOUT div out Control 31 16 RESERVED R 0 15 3 2 1 0 RESERVED CRYS CRYS CRYS _ _ _ DIV8 DIV3 DIV1 R 0 R 1 R 1 R 1 LEGEND R Read only n value after reset Table 9 13 CLKOUT CLKOUT div out Control Field Descriptions Bit Field Value Description 31 3 RESERVED Reserved 2 CRYS_DIV8 CLKOUT3 Enable CLKOUT3 is crystal frequency reference clock dvidied by 8 1 CRYS_DIV3 CLKOUT2 Enable CLKOUT2...

Page 133: ... only n value after reset Table 9 14 DEVICE_ID Device ID Field Descriptions Bit Field Value Description 31 28 DEVREV Device Revision 27 12 PARTNUM Device Part Number Unique JTAG ID 27 ARM Core ID 0 ARM processor 26 24 Capability 111 ARM Processor with J extension soft macrocell 23 20 Family 1001 0x9 19 12 Device Number 0010 0110 0x26 11 1 MFGR Manufacturer s JTAG ID Texas Instruments Mfg ID 0 RESE...

Page 134: ...ng control bit for VREF 25 22 TRESB4R2 Resistance trimming control bit for VREF 21 18 TRESB4R1 Resistance trimming control bit for VREF 17 11 TRIMBITS PNP transistor trimming control bit for VREF 10 PWD_BGZ Power Down of VREFF 0 power down 1 power Up 9 SPEED Faster operation of VREF transfer 0 Normal 1 Faster 8 TVINT TV cable connect status from DAC 0 Cable connected 1 Cable disconnected 7 PWD_VBU...

Page 135: ... 15 2 1 0 RESERVED GIO3_4 GIO1_2 R 0 R W 0 R W 0 LEGEND R Read only n value after reset Table 9 16 TIMER64_CTL Timer64 Input Control Field Descriptions Bit Field Value Description 31 2 RESERVED Reserved 1 GIO3_4 GIO3 OR GIO4 for input 0 gio3 for input 1 gio4 for input 0 GIO1_2 GIO1 OR GIO2 for input 0 gio1for input 1 gio2 for input SPRUFB3 September 2007 System Control Module 135 Submit Documentat...

Page 136: ...e 0 24MHz directly from crystal 1 12MHz after dividing 36 MHz crystal by 3 2 PLLC1 sysclk3 backup in case 27MHz crystal is used 3 _RESV 8 PHYCLKGD USB PHY Power and Clock Good 0 Phy power not ramped or PLL not locked 1 Phy power is good and PLL is locked 7 SESNDEN Session End Comparator enable 0 comparator disabled 1 comparator enabled 6 VBDTCTEN vbus comparator enable 0 comparators except session...

Page 137: ...ons Table 9 17 USB_PHY_CTRL USB PHY Control Field Descriptions continued Bit Field Value Description 0 PHYPDWN USB PHY power down control 0 PHY powered 1 PHY power off SPRUFB3 September 2007 System Control Module 137 Submit Documentation Feedback ...

Page 138: ...n 31 5 RESERVED Reserved 4 TIMER2_WDT TIMER2 Definition Normal vs WDT 0 TIMER2 is normal Timer 1 TIMER2 is WDT 3 2 DEV_SPEED Device speed grade eFuse status These bits indicate the device speed grades 1 PLL1_POSTDIV DM355 PLL1 post divider selection 0 Sets PLL1 post divider equal to 1 Setting this bit to 0 has no effect when DEV_SPEED equals 1 or 3 1 Sets PLL1 post divider equal to 2 0 AIM_WAIST A...

Page 139: ... 31 16 RESERVED R 0 15 7 6 4 3 2 0 RESERVED ARM_CFGP RESV ARM_DMAP R 0 R W 0x1 R 0 R W 0x1 LEGEND R Read only n value after reset Table 9 19 MSTPRI0 Master Priorities 0 Field Descriptions Bit Field Value Description 31 7 RESERVED Reserved 6 4 ARM_CFGP ARM CFG bus priority 3 RESV Reserved 2 0 ARM_DMAP ARM DMA priority SPRUFB3 September 2007 System Control Module 139 Submit Documentation Feedback ...

Page 140: ...PRI1 Master Priorities 1 31 16 RESERVED R 0 15 11 10 8 7 0 RESERVED USBP RESERVED R 0 R W 0x4 R 0 LEGEND R Read only n value after reset Table 9 20 MSTPRI1 Master Priorities 1 Field Descriptions Bit Field Value Description 31 11 RESERVED Reserved 10 8 USBP USB bus priority 7 0 RESERVED Reserved 140 System Control Module SPRUFB3 September 2007 Submit Documentation Feedback ...

Page 141: ...VENC_CLK_SRC 27MHz Input Source 0 PLL1 divided down SYSCLK3 1 External crystal 2 MXI2 MXO2 2 External crystal 1 MXI1 MXO1 3 RESV 4 DACCLKEN Enable Video DAC clock 0 disable 1 enable 3 VENCLKEN Enable VPBE Video Encoder clock 0 disable 1 enable 2 PCLK_INV Invert VPFE pixel clock PCLK 0 VENC clk mux and CCDC receive normal PCLK 1 VENC clk mux and CCDC receive inverted PCLK 1 0 VPSS_MUXSEL VPSS clock...

Page 142: ...r initiating Deep Sleep The ARM should 1 Prepare the device system for shutdown by placing DDR in auto_refresh and other powerdow housekeeping as necessary and then 2 Enable Deep Sleep Mode SLEEPENABLE 1 shut down 3 Inform the PMU MCU it is ready for Deep Sleep 4 Go into a loop polling for this SLEEPCOMPLETE bit to be set indicating it can proceed with restarting the DDR and other device modules N...

Page 143: ... GIO n Input 31 30 21 20 16 ENABLE RESERVED INTERVAL R W 0 R 0 R W 0 15 0 INTERVAL R W 0 LEGEND R Read only n value after reset Table 9 23 DEBOUNCE 8 De bounce for GIO n Input Field Descriptions Bit Field Value Description 31 ENABLE Debounce Enable 0 Debounce enable 1 Debounce Disable 30 21 RESERVED Reserved 20 0 INTERVAL Interval count for the debounce circuit SPRUFB3 September 2007 System Contro...

Page 144: ... N 0x37 LEGEND R Read only n value after reset Table 9 24 VTPIOCR VTP IO Control Field Descriptions Bit Field Value Description 31 16 RESERVED Reserved 15 READY VTP Ready Status 0 VTP not ready 1 VTP ready 14 VTPIOREADY VTP IO Ready Write 1 when VTP IO is ready 0 VTP IO not ready 1 VTP IO ready 13 CLR VTP Clear Write 0 to clear VTP flops 0 Clear VTP 1 Un clear VTP 12 9 RESERVED Reserved 8 PWRSAVE ...

Page 145: ...or or Watchdog Timer WDT Same effect as warm reset System Reset ARM emulator Resets all modules except memory and ARM emulation It is a soft reset that maintains memory contents and does not affect or reset clocks or power states Module Reset ARM software Resets a specific module Allows the ARM software to independently reset a module Module reset is intended as a debug tool not as a tool to use i...

Page 146: ... sequencing and reset timing requirements Warm reset is like POR except the ARM emulation circuitry is not reset Warm reset allows an ARM emulator to initiate chip reset using TRSTN and RESETN while remaining active during and after the reset sequence The following steps describe the warm reset sequence 1 Emulator drives TRSTN high and RESETN low to initiate warm reset 2 Emulator drives RESETN hig...

Page 147: ...the ICECrusher emulation module It is considered a soft reset i e memory is not reset None of the following modules are reset DDR EMIF PLL Controller PLLC Power and Sleep Controller PSC and emulation The following steps describe the system reset sequence 1 The emulator initiates system reset 2 The proper modules are reset 3 The system reset finishes the proper modules are reset and the CPU is out ...

Page 148: ...es the chip after reset For more information see Chapter 5 and Chapter 6 The default state of the PLLs is reflected by the default state of the register bits in the PLLC registers Only a subset of modules are enabled after reset by default Table 7 1 in Chapter 7 shows which modules are enabled after reset Furthermore as shown in Table 7 1 the following modules are enabled depending on the sampled ...

Page 149: ...ory Interface AEMIF Peripheral Reference Guide SPRU710 for more information on the AEMIF When AEMIF is enabled the wait state registers are reset to the slowest possible configuration which is 88 cycles per access 16 cycles of setup 64 cycles of strobe and 8 cycles of hold Thus with a 24 MHz clock at MXI MXO the AEMIF is configured to run at 4 MHz 88 which equals approximately 45 kHz See the Async...

Page 150: ...OT bit in the BOOTCFG register in the System Module in order to respond properly by executing any required device init bringing mDDR out of self refresh and branching to user entry point in mDDR The RBL supports 3 distinct boot modes BTSEL 1 0 00 ARM NAND Boot BTSEL 1 0 10 ARM MMC SD Boot BTSEL 1 0 11 ARM UART Boot If NAND boot fails then MMC SD mode is tried If MMC SD boot fails then MMC SD boot ...

Page 151: ...ad time ARM ROM Boot MMC SD Mode No support for a full firmware boot Instead copies a second stage Uwer Boot Loader UBL from MMC SD to ARm Internal RAM AIM and transfers control to the user softwaer Support for MMC SD Native protocol MMC SD SPI protocol is not supported Support for descriptor error detection and retry up to 24 times when loading UBL Support for up to 30KB UBL 32KB 2KB for RBL stac...

Page 152: ...than the normal ARM EMIF boot BTSEL 1 0 01 In this case control is passed to the ROM boot loader RBL The RBL then executes the proper mode after reading the state of the BTSEL 1 0 pins from the BOOTCFG register If the value in BTSEL 1 0 from the BOOTCFG register is 00 the NAND mode executes The outline of operations followed in the NAND mode is described in Figure 11 2 The NAND boot mode assumes t...

Page 153: ...BL signature If no valid UBL signature is found after searching 24 blocks the RBL will try to boot via MMC SD If a valid UBL is found the UBL descriptor is read and processed The descriptor gives the information required for loading and control transfer to the UBL The UBL is then read and processed The RBL may enable any combination of faster EMIF and I Cache operations based on information in the...

Page 154: ...der is present Note The first 32 bytes of AIM are the ARM s system interrupt vector table IVT 8 vectors 4 bytes each The UBL copy starts after the 32 byte IVT Different NAND boot mode options can be setting different MAGIC IDs in the UBL descriptor Table 11 2 lists the UBL signatures Table 11 2 UBL Signatures and Special Modes Mode Value Description UBL_MAGIC_SAFE 0x A1AC ED00 Safe boot mode UBL_M...

Page 155: ...C0 6 Syndrome3 syndromes10 3 0x03 6 syndromes10 2 0x3F0 4 Syndrome4 syndromes10 3 0x3FC 2 Syndrome5 syndromes10 4 0xFF Syndrome6 syndromes10 5 0x3F 2 syndromes10 4 0x300 8 Syndrome7 syndromes10 6 0x0F 4 syndromes10 5 0x3C0 6 Syndrome8 syndromes10 7 0x03 6 syndromes10 6 0x3F0 4 Syndrome9 syndromes10 7 0x3FC 2 Syndromex Write to NAND flash 8bit Data syndromes10 x Calculated by IP Algorithm to store ...

Page 156: ...p reset for Fast Boot Read the device Id of NAND and get the parameters for NAND from a table in ROM Initialize the NAND region according to the parameters for the NAND flash see Table 3 Search for the User Boot Loader magic number in the blocks after CIS IDI page CIS IDI is generally block 0 page 0 See Figure 11 8 Magic number is detected based on reading 0xA1ACEDxx in the first 32 bits of page 0...

Page 157: ...AM with hardware ECC error detection enabled If a 4 bit ECC read error is detected the UBL will correct the error via the ECC correction algorithm If the read fails due to any other error the descriptor search process begins anew in the next block after that in which the UBL descriptor was found for up to the first 24 blocks If no valid UBL descriptor is found after searching 24 blocks the RBL wil...

Page 158: ...sponding block number M 1 2 3 24 will be written to the last 32 bits of ARM internal memory 0x7FFC Configure the following based on boot descriptor I cache DMA fast EMIF options Starting block of UBL can be same block as UBL descriptor Starting page of UBL Number of NAND pages of UBL pages will be consecutive Entry point address absolute entry point address after loading UBL Copy N consecutive pag...

Page 159: ... UBL Entry point addr of UBL UBL magic number ID 32 bits Starting page of UBL Starting block of UBL 0xA1ACED00 0x00002100 0x00000013 0x00000001 0x00000002 UBL start addr 19 pages Block 1 Page 2 User boot loader UBL definition 0x0000 0x100000 0x0020 0x3FFF 0x13FFF IVT IRAM0 0x4000 0x781F 0x1781F IRAM0 0x14000 0x7FFF 0x17FFF ITCM DTCM Found magic number ROM bootloader copies UBL into IRAM0 Then tran...

Page 160: ...ound or NAND read error detected If no magic number found or NAND read error detected 11 2 1 2 NAND Device IDs Supported ARM ROM Boot Modes Figure 11 8 Descriptor Search for ARM NAND Boot Mode The list of IDs supported by ROM boot loader is shown in Table 11 3 with its characteristics Table 11 3 NAND IDs Supported Number of pages per Bytes per page Block shift value Device ID block including extra...

Page 161: ...ft value for address 22 Number of address cycles 5 Page shift 16 Note Fast NAND boot mode is not supported in DM355 Fast NAND boot mode is superseded by Deep Sleep mode Please use Deep Sleep mode instead of Fast NAND boot mode For information on Deep Sleep mode see Section 12 5 1 The DM355 has a power saving mode that is recoverable via a fast NAND boot mode The process works as follows The DM355 ...

Page 162: ...ialization and data transfers are done in native mode SPI mode is not supported After performing the MMC SD initialization sequence the RBL searches for the UBL Descriptor starting in block 0 If a valid UBL is not found in block 0 as determined by reading a proper UBL magic number the next block will be searched Searching will continue for up to 24 blocks This provision for additional searching is...

Page 163: ...MMC SD to IRAM Jump to user boot loader entry point in IRAM Copu user MAIN program in MMC SD to DDR Run MAIN program in DDR ROM boot loader User boot loader ARM ROM Boot Modes Figure 11 9 MMC SD Boot Mode Overview SPRUFB3 September 2007 Boot Modes 163 Submit Documentation Feedback ...

Page 164: ... format 0xA1ACEDxx and is in the first 32 bits of the block CRC error detection shall be enabled when reading the UBL Descriptor If a CRC read error is detected or the magic number is not valid the descriptor search process shall begin anew in the next block after that in which the UBL descriptor was just searched for up to the first 24 blocks When a valid UBL signature is found the corresponding ...

Page 165: ... up to M 24 When a valid UBL signature is found the corresponding block number M 1 2 3 24 will be written to the last 32 bits of ARM internal memory 0x7FFC Configure the following based on boot descriptor I Cache Starting block of UBL Number of blocks of UBL blocks will be consecutive Entry point address absolute entry point address after loading UBL Copy N consecutive blocks of UBL to AIM until e...

Page 166: ... addr of UBL UBL magic number ID 32 bits Starting block of UBL 0xA1ACED00 0x00002100 0x00000013 0x00000002 UBL start addr 19 blocks Block 2 User boot loader UBL definition 0x10000 0x13FFF 0x0000 0x3FFF 0x0020 IVT IRAM0 0x781F 0x4000 IRAM1 0x1781F 0x14000 0x7FFF 0x17FFF ITCM DTCM RBL stack space last 32 bits reserved for block number of valid descriptor Found magic number ROM bootloader copies UBL ...

Page 167: ...en the UART boot mode executes This mode enables a small program referred to here as a user boot loader UBL to be downloaded to the on chip ARM internal RAM via the on chip serial UART and executed A host program referred to as serial host utility program manages the interaction with RBL and provides a means for operator feedback and input The UART boot mode execution assumes the following UART se...

Page 168: ...re are three main receive sequences ACK 1KB CRC32 table and user boot loader UBL For each receive sequence a time out check is done in the RBL This means that if a timeout value is reached during the sequence the serial boot mode restarts from the beginning at which the RBL sends out the BOOTME message The error checking behavior for the UART receive mode is the same For each byte received if ther...

Page 169: ...mission The host utility asks you to reset the board UBL Variable The format for UBL is the same as NAND boot The CRC 32 check sum value is calculated for the UBL data and passed by the host serial utility The polynomial used for CRC32 is X 32 X 26 X 23 X 22 X 16 X 12 X 11 X 10 X 8 X 7 X 5 X 4 X 2 X 1 X 0 The RBL expects the data sent from the host utility to be in a perticular format This section...

Page 170: ...ding characters from the host to the DM355 UART RBL the host utility must insert a delay between each byte character equal to 1 ms Furthermore 5 ms delay must be inserted for each of the timing parameters shown in Figure 11 14 1 The delay time from BOOTME received until ACK sent 2 The delay time from ACK sent to CRC32 table data sent 3 The delay time from CRC32 table data sent to next CRC32 table ...

Page 171: ...clocks can be disabled to reduce switching power Module clock frequency scaling Module clock frequency can be scaled to reduce switching power PLL power down The PLLs can be powered down when not in use to reduce switching power ARM Sleep Mode ARM Wait for Interrupt sleep mode Disable ARM clock to reduce active power System Sleep Modes Deep Sleep Mode Stop all device clocks and power down internal...

Page 172: ...you can use this mode to reduce the core and module clock frequencies to very low maintenance levels without using the PLL during periods of very low system activity Furthermore you can power down the PLL when bypassing it to save additional active power Chapter 5 and Chapter 6 describe PLL bypass and PLL power down The ARM module cannot have its clock turned off on via the PSC module like other m...

Page 173: ...tinues to hold GIO0 low for a minimum of 500 ns until it desires to exit Deep Sleep mode The transition of GIO0 from high to low creates a clock pulse advancing the Deep Sleep state machine After this transition all clocks are stopped and then the internal oscillators are powered down At this point the DM355 is in Deep Sleep mode power is reduced to a minimum The Deep Sleep wake up process works a...

Page 174: ...entry point preserved in mDDR Note Refer to Section 11 2 1 3 for more information on Fast NAND Boot You can power down the USB Phy when it is not in use The USB Phy is powered down via the PHYPWDN bit in the USB_PHY_CTL register of the system control module USB_PHY_CTL is described in Chapter 9 Also see the TMS320DM355 DMSoC Univeral Serial Bus USB Controller Reference Guide SPRUED2 for more infor...

Page 175: ...ice and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyer...

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