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11.2.2 MMC/SD Boot Mode
ARM ROM Boot Modes
•
The RBL will copy a fast UBL from NAND to ARM internal memory and then transfer control to the fast
UBL. The fast UBL will reinitialize the DM355, bring mDDR out of self-refresh, and branch to an entry
point in mDDR.
The fast NAND boot mode is exactly the same as the normal NAND boot mode as described in the
section above, except for the following key differences:
•
The external pin DEEPSLEEPZ/GIO0 must be driven low during chip reset to select fast NAND boot
mode. When driven low during chip reset, the GIO0_RESET bit in the BOOTCFG register in the
System Module will indicate that Fast Boot must be executed. The RBL will read this bit to determine
whether to do a normal NAND boot or a fast NAND boot.
•
The RBL searches for a valid Fast Boot descriptor in blocks 25 through 48.
•
The Fast Boot descriptor magic number is of the format 0xF1FCEDxx. See tables below.
•
If no valid UBL descriptor is found after searching 24 blocks the RBL will try to boot via normal NAND
boot mode. The process for normal NAND boot mode is described in the sections above.
•
The fast UBL is expected to be small as faster than the normal UBL. The fast UBL is expected to
initialize the DM355 PLLs, clocks, pin-muxing configurations, etc, bring mDDR out of self-refresh, and
branch to an entry point in mDDR.
If the value is BTSEL[1:0] from the BOOTCFG register is ‘10’, the MMC/SD Boot mode will be executed.
The outline of operations followed in the MMC/SD mode is depicted in the figure below.
MMC/SD card needs to be powered on for boot up. After the boot up is finished, a GIO may be used as a
power switch to the MMC/SD card.
Initialization information, such as block size, is read from the CID and CSD registers of the MMC/SD
device. The CID and CSD registers of the MMC/SD device are read by the MMC/SD module in native
mode. All initialization and data transfers are done in native mode. SPI mode is not supported.
After performing the MMC/SD initialization sequence, the RBL searches for the UBL Descriptor starting in
block 0. If a valid UBL is not found in block 0, as determined by reading a proper UBL magic number, the
next block will be searched. Searching will continue for up to 24 blocks. This provision for additional
searching is made in case the first few consecutive blocks have errors. When a valid UBL descriptor is
found, the corresponding block number (from 1 to 24) shall be written to the last 32 bits of ARM internal
memory (0x7ffc-0x8000). This feature is provided as a basic debug mechanism. By reading these 32 bits
of memory, via JTAG for example, you can determine in which block the RBL found a valid UBL signature.
If no valid UBL signature is found after searching 24 blocks, the RBL will toggle GIO61 at 4Hz while
repeating the MMC/SD boot process from the beginning
The UBL descriptor, which gives the information required for loading and control transfer to the UBL, will
then be read and processed. Based on information in the UBL descriptor, the RBL may first enable
I-Cache operation. Once the user specified startup conditions are set, the RBL will copy the UBL into ARM
Internal RAM, starting at 0x0000:0020. Note that the actual copy will be done to the lower 30KB of the
TCM Data area: 0x10020 0x1781F.
The MMC/SD RBL will use the hardware CRC error detection capability to determine if a read error occurs
when reading the UBL including the UBL descriptor. If a read error occurs, the UBL copy will immediately
halt for that instance of magic number but the RBL will continue to search the block following that block in
which the magic number was found for another instance of a magic number. When a magic number is
found, the process is repeated. Using this retry process, the magic number and UBL can be duplicated up
to 24 times, giving significant redundancy and error resilience to MMC/SD read errors.
162
Boot Modes
SPRUFB3 – September 2007
