6.6.16 Clock Status Register (CKSTAT)
PLL Controller Register Map
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The clock status (CKSTAT) register is shown in
and described in
for PLLC1 and
PLLC2. CKSTAT shows the on/off status of the bypass clock (SYSCLKBP) and the auxiliary clock
(AUXCLK). PLLC2 does not use the auxiliary clock, so the AUXEN bit field is reserved for PLLC2.
Figure 6-18. Clock Status Register (CKSTAT)
31
4
3
2
1
0
Reserved
BPON
Reserved
AUXEN
R-0
R-1
R-0
R-1
LEGEND: R = Read, n = value at reset
Table 6-19. Clock Status Register (CKSTAT) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved
3
BPON
SYSCLKBP status. Shows the clock on/off status for SYSCLKBP.
0
Bypass clock is off
1
Bypass clock is on
2-1
Reserved
0
Reserved
0
AUXEN
AUXCLK status. Shows the clock on/off status for AUXCLK.
0
Aux clock is off
1
Aux clock is on
PLL Controllers (PLLCs)
60
SPRUFX7 – July 2008