6.6.7 PLL Controller Divider 2 Register (PLLDIV2)
www.ti.com
PLL Controller Register Map
The PLL controller divider 2 register (PLLDIV2) is shown in
and described in
for
PLLC1 and PLLC2. PLLDIV2 controls the divider for SYSCLK2. The divider for PLLC1 SYSCLK2 is fixed
(cannot be changed) to (/4). The divider for PLLC2 SYSCLK2 is fixed (cannot be changed) to (/2). For
PLLC1 and PLLC2, the divider must always be enabled (bit D2EN=1).
Figure 6-9. PLL Controller Divider 2 Register (PLLDIV2)
31
16
15
14
5
4
0
Reserved
D2EN
Reserved
RATIO
R-0
R/W-1
R-0
R-3
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 6-10. PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
Reserved
15
D2EN
Divider enable for SYSCLK2. For PLLC1 and PLLC2, this bit must always be set to 1.
0
Disable
1
Enable
14-5
Reserved
0
Reserved
4-0
RATIO
0-1Fh
Divider ratio for SYSCLK2. Ratio value = RATIO + 1
SPRUFX7 – July 2008
PLL Controllers (PLLCs)
51