6.6.6 PLL Controller Divider 1 Register (PLLDIV1)
PLL Controller Register Map
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The PLL controller divider 1 register (PLLDIV1) is shown in
and described in
for
PLLC1 and PLLC2. PLLDIV1 controls the divider for SYSCLK1. The divider for PLLC1 SYSCLK1 is fixed
(cannot be changed) to (/2). The divider for PLLC2 SYSCLK1 is fixed (cannot be changed) to (/1). For
PLLC1 the divider must always be endabled (bit D1EN=1).
Figure 6-8. PLL Controller Divider 1 Register (PLLDIV1)
31
16
15
14
5
4
0
Reserved
D1EN
Reserved
RATIO
R-0
R/W-1
R-0
R-1
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 6-9. PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
Reserved
15
D1EN
Divider enable for SYSCLK1. For PLLC1, this bit must always be set to 1. For PLLC2, this bit may
be set to 0 or 1.
0
Disable
1
Enable
14-5
Reserved
0
Reserved
4-0
RATIO
0-1Fh
Divider ratio for SYSCLK1. Ratio value = RATIO + 1
PLL Controllers (PLLCs)
50
SPRUFX7 – July 2008